2410iis.c

S3C2410上RS485驱动源码,用ADS1.2编译工程,已测试通过.内附文档.

#include "2410addr.h"
#include "2410lib.h"
#include "def.h"
#include "2410iis.h"
#include "INT.h"

void ChangeDMA2(void);
void IIS_PortSetting(void);
void _WrL3Addr(U8 data);
void _WrL3Data(U8 data,int halt);
void __irq DMA2_Done(void);
void __irq DMA2_Rec_Done(void);
void __irq RxInt(void);

#define L3C (1<<4)            //GPB4 = L3CLOCK
#define L3D (1<<3)            //GPB3 = L3DATA
#define L3M (1<<2)            //GPB2 = L3MODE

#define PLAY    0
#define RECORD  1
#define REC_LEN 0x50000       //327,680 Bytes

unsigned char *Buf,*_temp;
unsigned short *rec_buf;

volatile unsigned int size = 0;
volatile unsigned int   fs = 0;
volatile char    which_Buf = 1;
volatile char     Rec_Done = 0;
volatile char         mute = 1;

//------------------------------------------------------------------------------
//      SMDK2410 IIS Configuration
// GPB4 = L3CLOCK, GPB3 = L3DATA, GPB2 = L3MODE
// GPE4 = I2SSDO,  GPE3 = I2SSDI, GPE2 = CDCLK, GPE1 = I2SSCLK, GPE0 = I2SLRCK  
//------------------------------------------------------------------------------

//*********************[Iis_Tx] *********************************
void Iis_Tx(void)
{
    unsigned int save_B, save_E, save_PB, save_PE,i;
 
    ChangeClockDivider(1,1);        //1:2:4
    ChangeMPllValue(0x96,0x5,0x1);  //FCLK=135428571Hz, PCLK=3.385714MHz 
    save_B  = rGPBCON;       
    save_E  = rGPECON;       
    save_PB = rGPBUP;
    save_PE = rGPEUP;

    IIS_PortSetting();
  
  //  pISR_DMA2  = (unsigned)DMA2_Done;
    
   // rINTMSK    = ~(BIT_DMA2);   

      //Non-cacheable area = 0x31000000 ~ 0x33feffff
    Buf=(unsigned char *)WavBaseAddr;
    /*
    size = *(Buf+4) | *(Buf + 5)<<8 | *(Buf + 6)<<16 | *(Buf + 7)<<24;
    size = *(Buf + 0x28) | *(Buf + 0x29)<<8 | *(Buf + 0x2a)<<16 | *(Buf + 0x2b)<<24;
    size = (size>>1)<<1;
    fs   = *(Buf + 0x18) | *(Buf + 0x19)<<8 | *(Buf + 0x1a)<<16 | *(Buf + 0x1b)<<24;

    Init1341(PLAY);

      //DMA2 Initialize
    rDISRC2  = (int)(Buf + 0x30);               //0x31000030~(Remove header)      
    rDISRCC2 = (0<<1) + (0<<0);                 //The source is in the system bus(AHB), Increment      
    rDIDST2  = ((U32)IISFIFO);                  //IISFIFO    
    rDIDSTC2 = (1<<1) + (1<<0);                 //The destination is in the peripheral bus(APB), Fixed  
    rDCON2   = (1<<31)+(0<<30)+(0<<29)+(0<<28)+(0<<27)+(0<<24)+(1<<23)+(1<<22)+(1<<20)+(size/4);
      //Handshake, sync PCLK, TC int disable, single tx, single service, I2SSDO, I2S Rx request, 
      //noauto-reload, half-word,size/4.
    rDMASKTRIG2 = (0<<2) + (1<<1) + (0<<0);          //no-stop[2], DMA2 channel on[1], No-sw trigger[0] 

      //IIS Initialize
    if(fs==44100)               //11.2896MHz(256fs)
    {
        rIISPSR = (2<<5) + 2;   //Prescaler A,B=2 <- FCLK 135.4752MHz(1:2:4)
    }
    else                        //fs=22050, 5.6448MHz(256fs)
    {
        rIISPSR = (5<<5) + 5;   //Prescaler A,B=5 <- FCLK 135.4752MHz(1:2:4)     
    }
    rIISCON = (1<<5) + (1<<2) + (1<<1);         //Tx DMA enable[5], Rx idle[2], Prescaler enable[1]
      //Master mode[8],Tx mode[7:6],Low for Left Channel[5],IIS format[4],16bit ch.[3],CDCLK 256fs[2],IISCLK 32fs[1:0]
    rIISMOD = (0<<8) + (2<<6) + (0<<5) + (0<<4) + (1<<3) + (0<<2) + (1<<0);  
    rIISFCON = (1<<15) + (1<<13);        //Tx DMA,Tx FIFO --> start piling....
    
      //IIS Tx Start
    rIISCON |= 0x1;             //IIS Interface start
    while(i++<100);
    while((rDSTAT2 & 0xfffff)!=0x0)
    {
        ;;
    } 
   
    Delay(10);                   //For end of H/W Tx
    rIISCON      = 0x0;          //IIS Interface stop
    rDMASKTRIG2  = (1<<2);       //DMA2 stop
    rIISFCON     = 0x0;          //For FIFO flush
    
    size = 0;

    rGPBCON = save_B;
    rGPECON = save_E;
    rGPBUP  = save_PB;
    rGPEUP  = save_PE;

    rINTMSK |= (BIT_DMA2 );    
 //   ChangeMPllValue(0xa1,0x3,0x1);    // FCLK=202.8MHz
    
    */
    size = REC_LEN * 2;

    Init1341(PLAY);

    ISRVector[19] = DMA2_Done;
    rINTMSK   = ~(BIT_DMA2 );

      //DMA2 Initialize
    rDISRCC2 = (0<<1) + (0<<0);                         //AHB, Increment
    rDISRC2  = (int)rec_buf;                            //0x31000000
    rDIDSTC2 = (1<<1) + (1<<0);                         //APB, Fixed
    rDIDST2  = ((U32)IISFIFO);                          //IISFIFO
    rDCON2   = ((unsigned)1<<31)+(1<<23)+(1<<22)+(1<<20)+(size/2);
      //Handshake, sync PCLK, TC int, single tx, single service, I2SSDO, I2S request, 
      //Auto-reload, half-word, size/2
    rDMASKTRIG2 = (0<<2)+(1<<1)+0;    //No-stop, DMA2 channel on, No-sw trigger 

      //IIS Initialize
      //Master,Tx,L-ch=low,iis,16bit ch.,CDCLK=256fs,IISCLK=32fs
    rIISMOD = (0<<8) + (2<<6) + (0<<5) + (0<<4) + (1<<3) + (0<<2) + (1<<0);      
    rIISCON = (1<<5)+(0<<4)+(0<<3)+(1<<2)+(1<<1);
      //Tx DMA enable,Tx DMA disable,Tx not idle,Rx idle,prescaler enable,stop
    rIISFCON = (1<<15) + (1<<13);       //Tx DMA,Tx FIFO --> start piling....


    rIISCON |= 0x1;                   //IIS Tx Start
  
    while(i++<10000);
    while((rDSTAT2 & 0xfffff)!=0x0)
    {
        ;;
    } 
   
   
      //IIS Tx Stop
    Delay(10);               //For end of H/W Tx
    rIISCON     = 0x0;       //IIS stop
    rDMASKTRIG2 = (1<<2);    //DMA2 stop
    rIISFCON    = 0x0;       //For FIFO flush

    size = 0;

    rGPBCON = save_B;
    rGPECON = save_E;
    rGPBUP  = save_PB;
    rGPEUP  = save_PE;

    rINTMSK |= BIT_DMA2;
    

    ChangeMPllValue(0xa1,0x3,0x1);              // FCLK=202.8MHz
    mute = 1;
}


//**************** [ Record_Iis ] ***************************************
void Record_Iis(void)
{
    unsigned int save_B, save_E, save_PB, save_PE,i;

    ChangeClockDivider(1,1);        //1:2:4
    ChangeMPllValue(0x96,0x5,0x1);  //FCLK=135428571Hz, PCLK=3.385714MHz
    
    save_B  = rGPBCON;       
    save_E  = rGPECON;       
    save_PB = rGPBUP;
    save_PE = rGPEUP;

    IIS_PortSetting();
        
      //--- Record Buf initialize
      //Non-cacheable area = 0x31000000 ~ 0x33feffff
    rec_buf = (unsigned short*)WavBaseAddr;

    ISRVector[19]  = DMA2_Rec_Done;
    //pISR_EINT0 = (unsigned)Muting;
 
   // rINTSUBMSK=~(BIT_SUB_TC);
    rINTMSK = ~(BIT_DMA2);
    
    Init1341(RECORD);

      //--- DMA2 Initialize
    rDISRCC2 = (1<<1) + (1<<0);                         //APB, Fix  
    rDISRC2  = ((U32)IISFIFO);                          //IISFIFO
    rDIDSTC2 = (0<<1) + (0<<0);                         //PHB, Increment
    rDIDST2  = (int)rec_buf;                            //0x31000000 ~
    rDCON2   = ((unsigned)1<<31)+(1<<24)+(1<<23)+(1<<22)+(1<<20)+REC_LEN;
      //Handshake, sync PCLK, TC int, single tx, single service, I2SSDI, I2S Rx request, 
      //Off-reload, half-word, 0x50000 half word.
    rDMASKTRIG2 = (0<<2) + (1<<1) + 0;    //No-stop, DMA2 channel on, No-sw trigger

      //IIS Initialize
      //Master,Rx,L-ch=low,IIS,16bit ch,CDCLK=256fs,IISCLK=32fs
    rIISMOD = (0<<8) + (1<<6) + (0<<5) + (0<<4) + (1<<3) + (0<<2) + (1<<0);
    rIISPSR = (4<<5) + 4; //Prescaler_A/B=4 <- FCLK 112.896MHz(1:2:2) ,11.2896MHz(256fs),44.1KHz
    rIISCON = (0<<5) + (1<<4) + (1<<3) + (0<<2) + (1<<1);
      //Tx DMA disable,Rx DMA enable,Tx idle,Rx not idle,prescaler enable,stop
    rIISFCON = (1<<14) + (1<<12);     //Rx DMA,Rx FIFO --> start piling....


      //Rx start
    rIISCON |= 0x1;

    //while(!Rec_Done);
     while(i++<10000);
    while((rDSTAT2 & 0xfffff)!=0x0)
    {
        ;;
    } 
   
   
    rINTMSK|= BIT_DMA2;
  //  Rec_Done = 0;

      //IIS Stop
    Delay(10);                          //For end of H/W Rx
    rIISCON     = 0x0;                  //IIS stop
    rDMASKTRIG2 = (1<<2);               //DMA2 stop
    rIISFCON    = 0x0;                  //For FIFO flush
/*
    size = REC_LEN * 2;

    Init1341(PLAY);

    pISR_DMA2 = (unsigned)DMA2_Done;
    rINTMSK   = ~(BIT_DMA2 );

      //DMA2 Initialize
    rDISRCC2 = (0<<1) + (0<<0);                         //AHB, Increment
    rDISRC2  = (int)rec_buf;                            //0x31000000
    rDIDSTC2 = (1<<1) + (1<<0);                         //APB, Fixed
    rDIDST2  = ((U32)IISFIFO);                          //IISFIFO
    rDCON2   = (1<<31)+(0<<30)+(0<<29)+(0<<28)+(0<<27)+(0<<24)+(1<<23)+(1<<22)+(1<<20)+(size/2);
      //Handshake, sync PCLK, TC int, single tx, single service, I2SSDO, I2S request, 
      //Auto-reload, half-word, size/2
    rDMASKTRIG2 = (0<<2)+(1<<1)+0;    //No-stop, DMA2 channel on, No-sw trigger 

      //IIS Initialize
      //Master,Tx,L-ch=low,iis,16bit ch.,CDCLK=256fs,IISCLK=32fs
    rIISMOD = (0<<8) + (2<<6) + (0<<5) + (0<<4) + (1<<3) + (0<<2) + (1<<0);      
    rIISCON = (1<<5)+(0<<4)+(0<<3)+(1<<2)+(1<<1);
      //Tx DMA enable,Tx DMA disable,Tx not idle,Rx idle,prescaler enable,stop
    rIISFCON = (1<<15) + (1<<13);       //Tx DMA,Tx FIFO --> start piling....


    rIISCON |= 0x1;                   //IIS Tx Start
  
    while(i++<10000);
    while((rDSTAT2 & 0xfffff)!=0x0)
    {
        ;;
    } 
   
   
      //IIS Tx Stop
    Delay(10);               //For end of H/W Tx
    rIISCON     = 0x0;       //IIS stop
    rDMASKTRIG2 = (1<<2);    //DMA2 stop
    rIISFCON    = 0x0;       //For FIFO flush

    size = 0;

    rGPBCON = save_B;
    rGPECON = save_E;
    rGPBUP  = save_PB;
    rGPEUP  = save_PE;

    rINTMSK |= BIT_DMA2;
    

    ChangeMPllValue(0xa1,0x3,0x1);              // FCLK=202.8MHz
    mute = 1;
   */ 
}


//******************[ Init1341 ]**************************************
void Init1341(char mode)
{
    //Port Initialize
//----------------------------------------------------------
//   PORT B GROUP