s3c2410x.h

S3C2410上GPS模块的驱动代码.ADS1.2编译工程,附文档.

/**************************************************************************
*                                                                         *
*   PROJECT     : ARM port for UCOS-II                                    *
*                                                                         *
*   MODULE      : S3C2410X.h                                              *
*                                                                         *
*   AUTHOR      : Michael Anburaj                                         *
*                 URL  : http://geocities.com/michaelanburaj/             *
*                 EMAIL: [e-mail]                       *
*                                                                         *
*   PROCESSOR   : S3C2410X (32 bit ARM920T RISC core from Samsung)        *
*                                                                         *
*   IDE         : SDT 2.51 & ADS 1.2                                      *
*                                                                         *
*   DESCRIPTION :                                                         *
*   S3C2410X processor register definition header file.                   *
*                                                                         *
**************************************************************************/


#ifndef __S3C2410X_H__
#define __S3C2410X_H__







typedef unsigned char  BOOLEAN;
typedef unsigned char  INT8U;                    /* Unsigned  8 bit quantity                           */
typedef signed   char  INT8S;                    /* Signed    8 bit quantity                           */
typedef unsigned int   INT16U;                   /* Unsigned 16 bit quantity                           */
typedef signed   int   INT16S;                   /* Signed   16 bit quantity                           */
typedef unsigned long  INT32U;                   /* Unsigned 32 bit quantity                           */
typedef signed   long  INT32S;                   /* Signed   32 bit quantity                           */
typedef float          FP32;                     /* Single precision floating point                    */
typedef double         FP64;                     /* Double precision floating point                    */

typedef unsigned int   OS_STK;                   /* Each stack entry is 16-bit wide                    */
typedef unsigned int   OS_CPU_SR;                /* Define size of CPU status register (PSR = 32 bits) */

#define BYTE           INT8S                     /* Define data types for backward compatibility ...   */
#define UBYTE          INT8U                     /* ... to uC/OS V1.xx.  Not actually needed for ...   */
#define WORD           INT16S                    /* ... uC/OS-II.                                      */
#define UWORD          INT16U
#define LONG           INT32S
#define ULONG          INT32U


#ifdef __cplusplus
extern "C" {
#endif


/* ********************************************************************* */
/* Module configuration */

#define __mDate "04/01/03"             /* Revision date */
#define __mVer  "1.10"                 /* Revision number */

#define __mAuthor "Michael Anburaj, http://geocities.com/michaelanburaj/"
#define __mProcessor "S3c2410 (ARM920T from Samsung)"

#define __nConsolPort         0        /* Consol UART port number */
#define __nConsolBaud         115200   /* Consol Baud rate */
#define __nConsolFifoEn       True     /* FIFO Enable flag */

#define FCLK 202800000
#define HCLK (202800000/2)
#define PCLK (202800000/4)
#define UCLK PCLK

/* note: Reflect the changes in init.s */
#define FLASH_SADDR  0x00000000 /* Flash starting address */
#define SRAM_SADDR   0x40000000 /* SRAM starting address */
#define SRAM_SIZE    (4*1024)   /* 4K internal SRAM */
#define SFR_BADDR    0x48000000 /* SFR base address */

#define SDRAM_SADDR  0x30000000 /* SDRAM starting address */
#define SDRAM_SIZE   (64*1024*1024) /* 64M SDRAM */
#define ISR_BADDR    0x33ffff00 /* ISR vector table start address */

#define SRAM_EADDR   (SRAM_SADDR+SRAM_SIZE-1) /* SRAM end address */
#define SDRAM_EADDR  (SDRAM_SADDR+SDRAM_SIZE-1) /* SRAM end address */

/* These are from init.s, for stack analysis */
#define _SVC_STKSIZE  1024*20
#define _UND_STKSIZE  256
#define _ABT_STKSIZE  256
#define _IRQ_STKSIZE  1024*1
#define _FIQ_STKSIZE  256

#define STK_SIZE      (_SVC_STKSIZE+_UND_STKSIZE+_ABT_STKSIZE+_IRQ_STKSIZE+_FIQ_STKSIZE)

#define STK_SADDR     (ISR_BADDR-STK_SIZE)
/* These are from init.s, for stack analysis */


/* ********************************************************************* */
/* Module configuration */


/* ********************************************************************* */
/* Interface macro & data definition */

// Memory control 
#define rBWSCON    (*(volatile unsigned *)0x48000000) //Bus width & wait status
#define rBANKCON0  (*(volatile unsigned *)0x48000004) //Boot ROM control
#define rBANKCON1  (*(volatile unsigned *)0x48000008) //BANK1 control
#define rBANKCON2  (*(volatile unsigned *)0x4800000c) //BANK2 cControl
#define rBANKCON3  (*(volatile unsigned *)0x48000010) //BANK3 control
#define rBANKCON4  (*(volatile unsigned *)0x48000014) //BANK4 control
#define rBANKCON5  (*(volatile unsigned *)0x48000018) //BANK5 control
#define rBANKCON6  (*(volatile unsigned *)0x4800001c) //BANK6 control
#define rBANKCON7  (*(volatile unsigned *)0x48000020) //BANK7 control
#define rREFRESH   (*(volatile unsigned *)0x48000024) //DRAM/SDRAM refresh
#define rBANKSIZE  (*(volatile unsigned *)0x48000028) //Flexible Bank Size
#define rMRSRB6    (*(volatile unsigned *)0x4800002c) //Mode register set for SDRAM
#define rMRSRB7    (*(volatile unsigned *)0x48000030) //Mode register set for SDRAM


// USB Host


// INTERRUPT
#define rSRCPND     (*(volatile unsigned *)0x4a000000) //Interrupt request status
#define rINTMOD     (*(volatile unsigned *)0x4a000004) //Interrupt mode control
#define rINTMSK     (*(volatile unsigned *)0x4a000008) //Interrupt mask control
#define rPRIORITY   (*(volatile unsigned *)0x4a00000a) //IRQ priority control
#define rINTPND     (*(volatile unsigned *)0x4a000010) //Interrupt request status
#define rINTOFFSET  (*(volatile unsigned *)0x4a000014) //Interruot request source offset
#define rSUBSRCPND  (*(volatile unsigned *)0x4a000018) //Sub source pending
#define rINTSUBMSK  (*(volatile unsigned *)0x4a00001c) //Interrupt sub mask


// DMA
#define rDISRC0     (*(volatile unsigned *)0x4b000000) //DMA 0 Initial source
#define rDISRCC0    (*(volatile unsigned *)0x4b000004) //DMA 0 Initial source control
#define rDIDST0     (*(volatile unsigned *)0x4b000008) //DMA 0 Initial Destination
#define rDIDSTC0    (*(volatile unsigned *)0x4b00000c) //DMA 0 Initial Destination control
#define rDCON0      (*(volatile unsigned *)0x4b000010) //DMA 0 Control
#define rDSTAT0     (*(volatile unsigned *)0x4b000014) //DMA 0 Status
#define rDCSRC0     (*(volatile unsigned *)0x4b000018) //DMA 0 Current source
#define rDCDST0     (*(volatile unsigned *)0x4b00001c) //DMA 0 Current destination
#define rDMASKTRIG0 (*(volatile unsigned *)0x4b000020) //DMA 0 Mask trigger

#define rDISRC1     (*(volatile unsigned *)0x4b000040) //DMA 1 Initial source
#define rDISRCC1    (*(volatile unsigned *)0x4b000044) //DMA 1 Initial source control
#define rDIDST1     (*(volatile unsigned *)0x4b000048) //DMA 1 Initial Destination
#define rDIDSTC1    (*(volatile unsigned *)0x4b00004c) //DMA 1 Initial Destination control
#define rDCON1      (*(volatile unsigned *)0x4b000050) //DMA 1 Control
#define rDSTAT1     (*(volatile unsigned *)0x4b000054) //DMA 1 Status
#define rDCSRC1     (*(volatile unsigned *)0x4b000058) //DMA 1 Current source
#define rDCDST1     (*(volatile unsigned *)0x4b00005c) //DMA 1 Current destination
#define rDMASKTRIG1 (*(volatile unsigned *)0x4b000060) //DMA 1 Mask trigger

#define rDISRC2     (*(volatile unsigned *)0x4b000080) //DMA 2 Initial source
#define rDISRCC2    (*(volatile unsigned *)0x4b000084) //DMA 2 Initial source control
#define rDIDST2     (*(volatile unsigned *)0x4b000088) //DMA 2 Initial Destination
#define rDIDSTC2    (*(volatile unsigned *)0x4b00008c) //DMA 2 Initial Destination control
#define rDCON2      (*(volatile unsigned *)0x4b000090) //DMA 2 Control
#define rDSTAT2     (*(volatile unsigned *)0x4b000094) //DMA 2 Status
#define rDCSRC2     (*(volatile unsigned *)0x4b000098) //DMA 2 Current source
#define rDCDST2     (*(volatile unsigned *)0x4b00009c) //DMA 2 Current destination
#define rDMASKTRIG2 (*(volatile unsigned *)0x4b0000a0) //DMA 2 Mask trigger

#define rDISRC3     (*(volatile unsigned *)0x4b0000c0) //DMA 3 Initial source
#define rDISRCC3    (*(volatile unsigned *)0x4b0000c4) //DMA 3 Initial source control
#define rDIDST3     (*(volatile unsigned *)0x4b0000c8) //DMA 3 Initial Destination
#define rDIDSTC3    (*(volatile unsigned *)0x4b0000cc) //DMA 3 Initial Destination control
#define rDCON3      (*(volatile unsigned *)0x4b0000d0) //DMA 3 Control
#define rDSTAT3     (*(volatile unsigned *)0x4b0000d4) //DMA 3 Status
#define rDCSRC3     (*(volatile unsigned *)0x4b0000d8) //DMA 3 Current source
#define rDCDST3     (*(volatile unsigned *)0x4b0000dc) //DMA 3 Current destination
#define rDMASKTRIG3 (*(volatile unsigned *)0x4b0000e0) //DMA 3 Mask trigger


// CLOCK & POWER MANAGEMENT
#define rLOCKTIME   (*(volatile unsigned *)0x4c000000) //PLL lock time counter
#define rMPLLCON    (*(volatile unsigned *)0x4c000004) //MPLL Control
#define rUPLLCON    (*(volatile unsigned *)0x4c000008) //UPLL Control
#define rCLKCON     (*(volatile unsigned *)0x4c00000c) //Clock generator control
#define rCLKSLOW    (*(volatile unsigned *)0x4c000010) //Slow clock control
#define rCLKDIVN    (*(volatile unsigned *)0x4c000014) //Clock divider control


// LCD CONTROLLER
#define rLCDCON1    (*(volatile unsigned *)0x4d000000) //LCD control 1
#define rLCDCON2    (*(volatile unsigned *)0x4d000004) //LCD control 2
#define rLCDCON3    (*(volatile unsigned *)0x4d000008) //LCD control 3
#define rLCDCON4    (*(volatile unsigned *)0x4d00000c) //LCD control 4
#define rLCDCON5    (*(volatile unsigned *)0x4d000010) //LCD control 5
#define rLCDSADDR1  (*(volatile unsigned *)0x4d000014) //STN/TFT Frame buffer start address 1
#define rLCDSADDR2  (*(volatile unsigned *)0x4d000018) //STN/TFT Frame buffer start address 2
#define rLCDSADDR3  (*(volatile unsigned *)0x4d00001c) //STN/TFT Virtual screen address set
#define rREDLUT     (*(volatile unsigned *)0x4d000020) //STN Red lookup table
#define rGREENLUT   (*(volatile unsigned *)0x4d000024) //STN Green lookup table 
#define rBLUELUT    (*(volatile unsigned *)0x4d000028) //STN Blue lookup table
#define rDITHMODE   (*(volatile unsigned *)0x4d00004c) //STN Dithering mode
#define rTPAL       (*(volatile unsigned *)0x4d000050) //TFT Temporary palette
#define rLCDINTPND  (*(volatile unsigned *)0x4d000054) //LCD Interrupt pending
#define rLCDSRCPND  (*(volatile unsigned *)0x4d000058) //LCD Interrupt source
#define rLCDINTMSK  (*(volatile unsigned *)0x4d00005c) //LCD Interrupt mask
#define rLPCSEL     (*(volatile unsigned *)0x4d000060) //LPC3600 Control
#define PALETTE     0x4d000400                         //Palette start address


// NAND flash
#define rNFCONF     (*(volatile unsigned *)0x4e000000)      //NAND Flash configuration
#define rNFCMD      (*(volatile U8 *)0x4e000004)            //NADD Flash command
#define rNFADDR     (*(volatile U8 *)0x4e000008)            //NAND Flash address
#define rNFDATA     (*(volatile U8 *)0x4e00000c)            //NAND Flash data
#define rNFSTAT     (*(volatile unsigned *)0x4e000010)      //NAND Flash operation status
#define rNFECC      (*(volatile unsigned *)0x4e000014)      //NAND Flash ECC
#define rNFECC0     (*(volatile U8  *)0x4e000014)
#define rNFECC1     (*(volatile U8  *)0x4e000015)
#define rNFECC2     (*(volatile U8  *)0x4e000016)

// UART
#define rULCON0     (*(volatile unsigned *)0x50000000) //UART 0 Line control
#define rUCON0      (*(volatile unsigned *)0x50000004) //UART 0 Control
#define rUFCON0     (*(volatile unsigned *)0x50000008) //UART 0 FIFO control
#define rUMCON0     (*(volatile unsigned *)0x5000000c) //UART 0 Modem control
#define rUTRSTAT0   (*(volatile unsigned *)0x50000010) //UART 0 Tx/Rx status
#define rUERSTAT0   (*(volatile unsigned *)0x50000014) //UART 0 Rx error status
#define rUFSTAT0    (*(volatile unsigned *)0x50000018) //UART 0 FIFO status
#define rUMSTAT0    (*(volatile unsigned *)0x5000001c) //UART 0 Modem status
#define rUBRDIV0    (*(volatile unsigned *)0x50000028) //UART 0 Baud rate divisor

#define rULCON1     (*(volatile unsigned *)0x50004000) //UART 1 Line control
#define rUCON1      (*(volatile unsigned *)0x50004004) //UART 1 Control
#define rUFCON1     (*(volatile unsigned *)0x50004008) //UART 1 FIFO control
#define rUMCON1     (*(volatile unsigned *)0x5000400c) //UART 1 Modem control
#define rUTRSTAT1   (*(volatile unsigned *)0x50004010) //UART 1 Tx/Rx status
#define rUERSTAT1   (*(volatile unsigned *)0x50004014) //UART 1 Rx error status
#define rUFSTAT1    (*(volatile unsigned *)0x50004018) //UART 1 FIFO status