acpy2_start.s62

The DSPLIB is a collection of 39 high-level optimized DSP functions for the TMS320C64x device. This

;*          }
;*          else if (handle->params.srcElementIndex == 0) {
;*              //set as 1D2D transfer if only dstEIdx is used
;*              *opt |= 0x01A00000;
;*          }
;*          else if (handle->params.dstElementIndex == 0) {
;*              //set as 2D1D transfer if only srcEIdx is used
;*              *opt |= 0x05200000;
;*          }                               
;*      }
;*
;* NOTES
;*      This code is interrupt tolerant and is interruptible until a TCC in the
;*      CIPR becomes available for use, in the event of which interrupts will 
;*      become disabled.
;*
;* ENDIANNESS
;*      Little
;*
;* BEST CASE CYCLES
;*      100 cycles
;* 
;* CODESIZE
;*      512 bytes       
;*      
;******************************************************************************

        .include        acpy2_6x1x.h62
        .include        c62.h62

        .sect           ".text:ACPY2_start"
        .def            _ACPY2_start
        .ref            __ACPY2_TCCmask, __ACPY2_TCCTable, _ACPY2_configure

_ACPY2_start:
        
        MVKL    __ACPY2_TCCmask,A3
||      LDW     *+A4(IDMA2_O_XTYPE),A1      ;Load the transfer type
||      MV      A4,B5                       ;duplicate handle for parallel LDWs

        MVKH    __ACPY2_TCCmask,A3
        LDW     *+A4(IDMA2_O_DELEIDX),A8    ;Load the dst element index
||      LDW     *+B5(IDMA2_O_SELEIDX),B7    ;Load the src element index

        LDW     *+A4(IDMA2_O_ESIZE),A2      ;Load the element size
||      LDW     *+B5(IDMA2_O_SFRMIDX),B9    ;Load the src frame index


        NOP     3
        
        OR      A8,B7,B0        ;B0 = Is element index used?
  [ B0] B       elemIdxAdjust
||[!B0] LDW     *+B5(IDMA2_O_DFRMIDX),B5    ;Load the dst frame index
  [ B0] LDW     *+A4(IDMA2_O_IDX),B5     
         
        LDW     *A3,A3          ;A3 contains ACPY2_TCCmask       

||      MVKL    0x1a0ffe4,A9    ;A9 contains address of CIPR    

        ;QDMA base reg = _EDMA_QOPT_ADDR (was an MVKL inst. originally)
||      ZERO    A7
        NOP     

  [!B0] OR      B4,A6,B0        ;B0 = alignment (dst|src)
||      MVKH    0x1a0ffe4,A9
||[!B0] LDW     *+A4(IDMA2_O_IDX),A8     
        MV      B6,A0           ;A0 will contain the cnt in # bytes
||      LDW     *+A4(IDMA2_O_OPT),B8     ;B8 contains handle->config.opt
        CMPEQ   A2,2,B2
||      OR      B5,B9,B5        ;B5 = alignment (frmIdx)
  [ B2] B       elem32          ;branch if Elem_size is 32

        CMPEQ   A2,1,B2
  [ B2] B       elem16          ;branch if Elem_size is 16
        ZERO    A5
||[ B2] SHL     A0,1,A0
  [ A1] OR      B5,B0,B0        ;B0 = alignment (dst|src|frmidx) for 32bit    
        AND     B0,0x1,B1       ;Check the LSB in alignment for 32bit case

        OR      A0,B0,B0        ;B0 = alignment (dst|src|frmidx|cnt)
        AND     B0,0x1,B1       ;Check the LSB in alignment
                
elem8:                          ;Element Size 8
        B       pollingLoop             
||[!B1] SHR     B6,1,B6         ;adjust count for 16/32 bit (alignment x0)
  [!B1] MVKH    0x08000000,A5   ;Mask for 16 bit transfer in A5
||[!B1] AND     B0,0x2,B0       ;check the second bit
  [!B1] CLR     B8,27,28,B8     ;clear the 2 bits related to element size
  [!B1] OR      B8,A5,B8        ;adjust opt for 16 bit transfer (alignment 10)
||[ B1] MVK     0x1,B0          ;8 bit transfer => Do not evaluate next 2 lines
        
  [!B0] SHR     B6,1,B6         ;adjust count for 16 bit xfer (alignment 10)
  [!B0] CLR     B8,27,28,B8     ;adjust opt for 32 bit xfer
||      MV      A1,A5           ;make a copy of xType
        
elem16:                         ;Element Size 16        
        B       pollingLoop             
||[!B1] AND     B0,0x2,B0       ;check the second bit
||[ B1] SHL     B6,1,B6         ;adjust count for 8 bit xfer (bad alignment)
  [ B1] CLR     B8,27,28,B8     ;clear the 2 bits for element size
  [ B1] MVKH    0x10000000,A5   ;Mask for 8 bit transfer in A5
  [ B1] OR      B8,A5,B8        ;8 bit transfer (bad alignment)
||[ B1] MVK     0x1,B0          ;8 bit transfer => do not evaluate next 2 lines
        
  [!B0] CLR     B8,27,28,B8     ;32 bit transfer (alignment 00)
  [!B0] SHR     B6,1,B6         ;adjust count for 32 bit xfer (alignment 00)
||      MV      A1,A5           ;make a copy of xType
        
elem32:                         ;Element Size 32, check for bad alignment       
  [ B1] SHL     B6,2,B6         ;adjust count for 8 bit xfer (bad alignment)
  [ B1] MVKH    0x10000000,A5   ;Mask for 8 bit transfer in A5
  [ B1] OR      B8,A5,B8        ;8 bit transfer (bad alignment)
||[!B1] AND     B0,0x2,B0       ;check the second bit
  [!B1] MVKH    0x08000000,A5   ;Mask for 16 bit transfer in A5
||[ B1] ZERO    B0              ;8 bit transfer => do not evaluate next 2 lines
    
  [ B0] SHL     B6,1,B6         ;adjust count for 16 bit xfer (bad alignment)
||[ B0] OR      B8,A5,B8        ;16 bit transfer (bad alignment)
||      MV      A1,A5           ;make a copy of xType
                                
pollingLoop:

        ;Disable interrupts     
        B       dummyLabel
||      LDW     *A9,A0          ;CIPR is in A0
||      MVKL    __ACPY2_TCCTable,B2      ;Set up regs to update TCC Table
        MVC     CSR,B1          ;B1 contains old CSR value
||      MVKH    0x2000000,A7    ;QDMA base register = (_EDMA_QOPT_ADDR)
        AND     B1,~GIE,A2
        MVC     A2,CSR          ;Clear GIE bit
        NOP     
        AND     A0,A3,A2        ;A2 == 1 implies a TCC is available
                
dummyLabel:
  [!A2] B       pollingLoop     ;Branch until a TCC is available
||[!A2] MVC     B1,CSR          ;Reenable interrupts for a short time
||[!A2] ZERO    A1              ;Avoid executing the last statement in loop
  [ A2] STW     A6,*+A7(CONFIG_O_DST)
||[ A2] MVK     0x001f,A3       
||[ A2] LMBD    1,A2,B0
  [ A2] SUB     A3,B0,B0        ;B0 contains the left-most TCC bit set in CIPR
||[ A2] MVK     0x0001,B7       ;B0 contains the number of the TCC available
||[ A2] STW     B4,*+A7(CONFIG_O_SRC)
||[ A2] MV      A5,A1           ;Putting xType into cond. reg.
        
  [ A2] SHL     B7,B0,B7
||[ A2] STW     B0,*+A4(IDMA2_O_LASTTCC) ;Update last TCC used for this handle
  [ A2] STW     B7,*A9          ;Write to CIPR to reset TCC
||[ A2] MVKH    __ACPY2_TCCTable,B2      ;Set up regs to update TCC Table
||[ A2] MV      B0,B5

  [ A1] LDW     *+A4(IDMA2_O_CNT),A0     ;A0 contains (handle->config).cnt 

        ;Set all QDMA registers and return                      
        B       B3              ;function return                
||      STW     A4,*+B2[B5]     ;Update TCCtable
        SHL     B0,16,B0        ;TCC number is shifted to upper 16 bits
        STW     A8,*+A7(CONFIG_O_IDX)

||      OR      B0,B8,B8        ;B8 = (handle->config).opt | (ACPY2_temp << 16)
        STW     B8,*+A7(CONFIG_O_OPT)
        
  [ A1] ADD     B6,A0,B6        ;B6 now contains the value for QSCNT
||      MVC     B1,CSR          ;Reenable interrupts

        STW     B6,*+A7(CONFIG_O_SCNT)    ;Write to QSCNT
        



elemIdxAdjust:
        ;When element index is used, go with the conservative approach
        ; to schedule everything as 8-bit transfers to ensure there is no
        ; alignment issues
        MV      A2,B2           ;elemSize in B2
||      SUB     B6,1,B6         ;numFrames = 0 implies 1 frame transferred
        ZERO    A5
||      SHL     B2,1,B2         
        MVKH    0x10000000,A5   ;Mask for 8 bit transfer in A5
||[!B2] ADD     B2,1,B2         ;B2 = {1 (8bit), 2 (16bit), 4 (32bit)} 
||      SHL     B6,16,B6        ;new numFrames = cnt
        MV      B7,B0           ;srcEIdx in B0
||      MV      A8,B1           ;dstEIdx in B1  
||      SUB     B5,B2,B5        
        CLR     B8,27,28,B8     ;clear the 2 bits for element size
||      SHL     B5,16,A8        ;new FIdx = EIdx - esize
        OR      B8,A5,B8        ;8 bit transfer 
||      ADD     B6,B2,B6        ;new cnt = esize  
        
        B       pollingLoop     ;return to normal processing

        ;set as 2D2D transfer if both EIdx are set
||      ADD     B0,B1,B2
||      CLR     B8,24,25,B8     ;clear the bits for addressing type
        CMPEQ   B2,B1,B2
||      CLR     B8,21,22,B8     ;clear the bits for addressing type
||      ZERO    B7       
  [!B2] MVKH    0x05A00000,B7
        ;set as 1D2D transfer if only dstEIdx is used   
  [!B0] MVKH    0x01A00000,B7
        ;set as 2D1D transfer if only srcEIdx is used
  [!B1] MVKH    0x05200000,B7 

        OR      B7,B8,B8
        
||      MV      A1,A5