📄 t01.asm
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;****************************************************************************
; Filename T01.asm
; Project T01.dav
;----------------------------------------------------------------------------
; Description This file contains the assembler formatted information
; about the actual project values. It will be used by your
; programming environment.
;
; PLEASE DO NOT MODIFY THIS FILE !
;
;----------------------------------------------------------------------------
; Date 2008-7-13 19:11:59
;
;****************************************************************************
; RMAP=x -CPU Accumulator Register
ACC_ACC0 SET 0
ACC_ACC1 SET 0
ACC_ACC2 SET 0
ACC_ACC3 SET 0
ACC_ACC4 SET 0
ACC_ACC5 SET 0
ACC_ACC6 SET 0
ACC_ACC7 SET 0
; RMAP=0 PAGE=1-ADC Channel 0 Control Register
ADC_CHCTR0_LCC SET 0
ADC_CHCTR0_RESRSEL SET 0
; RMAP=0 PAGE=1-ADC Channel 1 Control Register
ADC_CHCTR1_LCC SET 0
ADC_CHCTR1_RESRSEL SET 0
; RMAP=0 PAGE=1-ADC Channel 2 Control Register
ADC_CHCTR2_LCC SET 0
ADC_CHCTR2_RESRSEL SET 0
; RMAP=0 PAGE=1-ADC Channel 3 Control Register
ADC_CHCTR3_LCC SET 0
ADC_CHCTR3_RESRSEL SET 0
; RMAP=0 PAGE=1-ADC Channel 4 Control Register
ADC_CHCTR4_LCC SET 0
ADC_CHCTR4_RESRSEL SET 0
; RMAP=0 PAGE=1-ADC Channel 5 Control Register
ADC_CHCTR5_LCC SET 0
ADC_CHCTR5_RESRSEL SET 0
; RMAP=0 PAGE=1-ADC Channel 6 Control Register
ADC_CHCTR6_LCC SET 0
ADC_CHCTR6_RESRSEL SET 0
; RMAP=0 PAGE=1-ADC Channel 7 Control Register
ADC_CHCTR7_LCC SET 0
ADC_CHCTR7_RESRSEL SET 0
; RMAP=0 PAGE=5-ADC Channel Interrupt Clear Register
ADC_CHINCR_CHINC0 SET 0
ADC_CHINCR_CHINC1 SET 0
ADC_CHINCR_CHINC2 SET 0
ADC_CHINCR_CHINC3 SET 0
ADC_CHINCR_CHINC4 SET 0
ADC_CHINCR_CHINC5 SET 0
ADC_CHINCR_CHINC6 SET 0
ADC_CHINCR_CHINC7 SET 0
; RMAP=0 PAGE=5-ADC Channel Interrupt Flag Register
ADC_CHINFR_CHINF0 SET 0
ADC_CHINFR_CHINF1 SET 0
ADC_CHINFR_CHINF2 SET 0
ADC_CHINFR_CHINF3 SET 0
ADC_CHINFR_CHINF4 SET 0
ADC_CHINFR_CHINF5 SET 0
ADC_CHINFR_CHINF6 SET 0
ADC_CHINFR_CHINF7 SET 0
; RMAP=0 PAGE=5-ADC Channel Interrupt Node Pointer Register
ADC_CHINPR_CHINP0 SET 0
ADC_CHINPR_CHINP1 SET 0
ADC_CHINPR_CHINP2 SET 0
ADC_CHINPR_CHINP3 SET 0
ADC_CHINPR_CHINP4 SET 0
ADC_CHINPR_CHINP5 SET 0
ADC_CHINPR_CHINP6 SET 0
ADC_CHINPR_CHINP7 SET 0
; RMAP=0 PAGE=5-ADC Channel Interrupt Set Register
ADC_CHINSR_CHINS0 SET 0
ADC_CHINSR_CHINS1 SET 0
ADC_CHINSR_CHINS2 SET 0
ADC_CHINSR_CHINS3 SET 0
ADC_CHINSR_CHINS4 SET 0
ADC_CHINSR_CHINS5 SET 0
ADC_CHINSR_CHINS6 SET 0
ADC_CHINSR_CHINS7 SET 0
; RMAP=0 PAGE=6-ADC Source 1 Conversion Request Control Register
ADC_CRCR1_CH4 SET 0
ADC_CRCR1_CH5 SET 0
ADC_CRCR1_CH6 SET 0
ADC_CRCR1_CH7 SET 0
; RMAP=0 PAGE=6-ADC Source 1 Conversion Request Mode Register
ADC_CRMR1_0 SET 0
ADC_CRMR1_CLRPND SET 0
ADC_CRMR1_ENGT SET 0
ADC_CRMR1_ENSI SET 0
ADC_CRMR1_ENTR SET 0
ADC_CRMR1_LDEV SET 0
ADC_CRMR1_RSV SET 0
ADC_CRMR1_SCAN SET 0
; RMAP=0 PAGE=6-ADC Source 1 Conversion Request Pending Register
ADC_CRPR1_CHP4 SET 0
ADC_CRPR1_CHP5 SET 0
ADC_CRPR1_CHP6 SET 0
ADC_CRPR1_CHP7 SET 0
; RMAP=0 PAGE=0-ADC External Trigger Control Register
ADC_ETRCR_ETRSEL0 SET 0
ADC_ETRCR_ETRSEL1 SET 0
ADC_ETRCR_SYNEN0 SET 0
ADC_ETRCR_SYNEN1 SET 0
; RMAP=0 PAGE=5-ADC Event Interrupt Clear Register
ADC_EVINCR_EVINC0 SET 0
ADC_EVINCR_EVINC1 SET 0
ADC_EVINCR_EVINC4 SET 0
ADC_EVINCR_EVINC5 SET 0
ADC_EVINCR_EVINC6 SET 0
ADC_EVINCR_EVINC7 SET 0
; RMAP=0 PAGE=5-ADC Event Interrupt Flag Register
ADC_EVINFR_EVINF0 SET 0
ADC_EVINFR_EVINF1 SET 0
ADC_EVINFR_EVINF4 SET 0
ADC_EVINFR_EVINF5 SET 0
ADC_EVINFR_EVINF6 SET 0
ADC_EVINFR_EVINF7 SET 0
; RMAP=0 PAGE=5-ADC Event Interrupt Node Pointer Register
ADC_EVINPR_EVINP0 SET 0
ADC_EVINPR_EVINP1 SET 0
ADC_EVINPR_EVINP4 SET 0
ADC_EVINPR_EVINP5 SET 0
ADC_EVINPR_EVINP6 SET 0
ADC_EVINPR_EVINP7 SET 0
; RMAP=0 PAGE=5-ADC Event Interrupt Set Flag Register
ADC_EVINSR_EVINS0 SET 0
ADC_EVINSR_EVINS1 SET 0
ADC_EVINSR_EVINS4 SET 0
ADC_EVINSR_EVINS5 SET 0
ADC_EVINSR_EVINS6 SET 0
ADC_EVINSR_EVINS7 SET 0
; RMAP=0 PAGE=0-ADC Global Control Register
ADC_GLOBCTR_ANON SET 0
ADC_GLOBCTR_CTC SET 3
ADC_GLOBCTR_DW SET 0
; RMAP=0 PAGE=0-ADC Global Status Register
ADC_GLOBSTR_BUSY SET 0
ADC_GLOBSTR_CHNR SET 0
ADC_GLOBSTR_SAMPLE SET 0
; RMAP=0 PAGE=0-ADC Input Class 0 Register
ADC_INPCR0_STC SET 0
; RMAP=0 PAGE=0-ADC Limit Check Boundary Register
ADC_LCBR_BOUND0 SET 7
ADC_LCBR_BOUND1 SET 11
; RMAP=0 -ADC Page Register
ADC_PAGE_OP SET 0
ADC_PAGE_PAGE SET 0
ADC_PAGE_STNR SET 0
; RMAP=0 PAGE=0-ADC Priority and Arbitration Register
ADC_PRAR_ARBM SET 0
ADC_PRAR_ASEN0 SET 0
ADC_PRAR_ASEN1 SET 0
ADC_PRAR_CSM0 SET 0
ADC_PRAR_CSM1 SET 0
ADC_PRAR_PRIO0 SET 0
ADC_PRAR_PRIO1 SET 0
; RMAP=0 PAGE=6-ADC Source 0 Queue 0 Register
ADC_Q0R0_ENSI SET 0
ADC_Q0R0_EXTR SET 0
ADC_Q0R0_REQCHNR SET 0
ADC_Q0R0_RF SET 0
ADC_Q0R0_V SET 0
; RMAP=0 PAGE=6-ADC Source 0 Queue Backup Register
ADC_QBUR0_ENSI SET 0
ADC_QBUR0_EXTR SET 0
ADC_QBUR0_REQCHNR SET 0
ADC_QBUR0_RF SET 0
ADC_QBUR0_V SET 0
; RMAP=0 PAGE=6-ADC Source 0 Queue Input Register
ADC_QINR0_ENSI SET 0
ADC_QINR0_EXTR SET 0
ADC_QINR0_REQCHNR SET 0
ADC_QINR0_RF SET 0
; RMAP=0 PAGE=6-ADC Source 0 Queue Mode Register
ADC_QMR0_0 SET 0
ADC_QMR0_CEV SET 0
ADC_QMR0_CLRV SET 0
ADC_QMR0_ENGT SET 0
ADC_QMR0_ENTR SET 0
ADC_QMR0_FLUSH SET 0
ADC_QMR0_TREV SET 0
; RMAP=0 PAGE=6-ADC Source 0 Queue Status Register
ADC_QSR0_EMPTY SET 0
ADC_QSR0_EV SET 0
ADC_QSR0_FILL SET 0
ADC_QSR0_RSV SET 0
; RMAP=0 PAGE=4-ADC Result 0 Control Register
ADC_RCR0_DRCTR SET 0
ADC_RCR0_IEN SET 0
ADC_RCR0_VFCTR SET 0
ADC_RCR0_WFR SET 0
; RMAP=0 PAGE=4-ADC Result 1 Control Register
ADC_RCR1_DRCTR SET 0
ADC_RCR1_IEN SET 0
ADC_RCR1_VFCTR SET 0
ADC_RCR1_WFR SET 0
; RMAP=0 PAGE=4-ADC Result 2 Control Register
ADC_RCR2_DRCTR SET 0
ADC_RCR2_IEN SET 0
ADC_RCR2_VFCTR SET 0
ADC_RCR2_WFR SET 0
; RMAP=0 PAGE=4-ADC Result 3 Control Register
ADC_RCR3_DRCTR SET 0
ADC_RCR3_IEN SET 0
ADC_RCR3_VFCTR SET 0
ADC_RCR3_WFR SET 0
; RMAP=0 PAGE=2-ADC Result 0 Register High
ADC_RESR0H_RESULT SET 0
; RMAP=0 PAGE=2-ADC Result 0 Register Low
ADC_RESR0L_CHNR SET 0
ADC_RESR0L_DRC SET 0
ADC_RESR0L_RESULT SET 0
ADC_RESR0L_VF SET 0
; RMAP=0 PAGE=2-ADC Result 1 Register High
ADC_RESR1H_RESULT SET 0
; RMAP=0 PAGE=2-ADC Result 1 Register Low
ADC_RESR1L_CHNR SET 0
ADC_RESR1L_DRC SET 0
ADC_RESR1L_RESULT SET 0
ADC_RESR1L_VF SET 0
; RMAP=0 PAGE=2-ADC Result 2 Register High
ADC_RESR2H_RESULT SET 0
; RMAP=0 PAGE=2-ADC Result 2 Register Low
ADC_RESR2L_CHNR SET 0
ADC_RESR2L_DRC SET 0
ADC_RESR2L_RESULT SET 0
ADC_RESR2L_VF SET 0
; RMAP=0 PAGE=2-ADC Result 3 Register High
ADC_RESR3H_RESULT SET 0
; RMAP=0 PAGE=2-ADC Result 3 Register Low
ADC_RESR3L_CHNR SET 0
ADC_RESR3L_DRC SET 0
ADC_RESR3L_RESULT SET 0
ADC_RESR3L_VF SET 0
; RMAP=0 PAGE=3-ADC Result 0 View A Register High
ADC_RESRA0H_RESULT SET 0
; RMAP=0 PAGE=3-ADC Result 0 View A Register Low
ADC_RESRA0L_CHNR SET 0
ADC_RESRA0L_DRC SET 0
ADC_RESRA0L_RESULT SET 0
ADC_RESRA0L_VF SET 0
; RMAP=0 PAGE=3-ADC Result 1 View A Register High
ADC_RESRA1H_RESULT SET 0
; RMAP=0 PAGE=3-ADC Result 1 View A Register Low
ADC_RESRA1L_CHNR SET 0
ADC_RESRA1L_DRC SET 0
ADC_RESRA1L_RESULT SET 0
ADC_RESRA1L_VF SET 0
; RMAP=0 PAGE=3-ADC Result 2 View A Register High
ADC_RESRA2H_RESULT SET 0
; RMAP=0 PAGE=3-ADC Result 2 View A Register Low
ADC_RESRA2L_CHNR SET 0
ADC_RESRA2L_DRC SET 0
ADC_RESRA2L_RESULT SET 0
ADC_RESRA2L_VF SET 0
; RMAP=0 PAGE=3-ADC Result 3 View A Register High
ADC_RESRA3H_RESULT SET 0
; RMAP=0 PAGE=3-ADC Result 3 View A Register Low
ADC_RESRA3L_CHNR SET 0
ADC_RESRA3L_DRC SET 0
ADC_RESRA3L_RESULT SET 0
ADC_RESRA3L_VF SET 0
; RMAP=0 PAGE=4-ADC Valid Flag Clear Register
ADC_VFCR_VFC0 SET 0
ADC_VFCR_VFC1 SET 0
ADC_VFCR_VFC2 SET 0
ADC_VFCR_VFC3 SET 0
; RMAP=0 PAGE=0-SCU Baud Rate Control Register
BCON_BGSEL SET 0
BCON_BRDIS SET 0
BCON_BRPRE SET 0
BCON_R SET 0
; RMAP=0 PAGE=0-SCU Baud Rate Timer/Reload Register
BG_BR_VALUE SET 1
; RMAP=x -CPU B Register
B_B0 SET 0
B_B1 SET 0
B_B2 SET 0
B_B3 SET 0
B_B4 SET 0
B_B5 SET 0
B_B6 SET 0
B_B7 SET 0
; RMAP=0 -MultiCAN Serial Channel Control Register
CAN_ADCON_AUAD SET 0
CAN_ADCON_BSY SET 0
CAN_ADCON_RWEN SET 0
CAN_ADCON_V0 SET 0
CAN_ADCON_V1 SET 0
CAN_ADCON_V2 SET 0
CAN_ADCON_V3 SET 0
; RMAP=0 -MultiCAN Baud Rate Control Register
CAN_ADH_CA10 SET 0
CAN_ADH_CA11 SET 0
CAN_ADH_CA12 SET 0
CAN_ADH_CA13 SET 0
; RMAP=0 -MultiCAN Serial Data Buffer Register
CAN_ADL_CA2 SET 0
CAN_ADL_CA3 SET 0
CAN_ADL_CA4 SET 0
CAN_ADL_CA5 SET 0
CAN_ADL_CA6 SET 0
CAN_ADL_CA7 SET 0
CAN_ADL_CA8 SET 0
CAN_ADL_CA9 SET 0
; RMAP=0 -MultiCAN CAN Data Register 0
CAN_DATA0_CD[7:0] SET 0
; RMAP=0 -MultiCAN CAN Data Register 1
CAN_DATA1_CD[15:8] SET 0
; RMAP=0 -MultiCAN CAN Data Register 2
CAN_DATA2_CD SET 0
; RMAP=0 -MultiCAN CAN Data Register 3
CAN_DATA3_CD SET 0
; List Register 0
CAN_LIST0_0 SET 0
CAN_LIST0_BEGIN SET 0
CAN_LIST0_EMPTY SET 0
CAN_LIST0_END SET 0
CAN_LIST0_SIZE SET 0
; List Register 1
CAN_LIST1_0 SET 0
CAN_LIST1_BEGIN SET 0
CAN_LIST1_EMPTY SET 0
CAN_LIST1_END SET 0
CAN_LIST1_SIZE SET 0
; List Register 2
CAN_LIST2_0 SET 0
CAN_LIST2_BEGIN SET 0
CAN_LIST2_EMPTY SET 0
CAN_LIST2_END SET 0
CAN_LIST2_SIZE SET 0
; List Register 3
CAN_LIST3_0 SET 0
CAN_LIST3_BEGIN SET 0
CAN_LIST3_EMPTY SET 0
CAN_LIST3_END SET 0
CAN_LIST3_SIZE SET 0
; List Register 4
CAN_LIST4_0 SET 0
CAN_LIST4_BEGIN SET 0
CAN_LIST4_EMPTY SET 0
CAN_LIST4_END SET 0
CAN_LIST4_SIZE SET 0
; List Register 5
CAN_LIST5_0 SET 0
CAN_LIST5_BEGIN SET 0
CAN_LIST5_EMPTY SET 0
CAN_LIST5_END SET 0
CAN_LIST5_SIZE SET 0
; List Register 6
CAN_LIST6_0 SET 0
CAN_LIST6_BEGIN SET 0
CAN_LIST6_EMPTY SET 0
CAN_LIST6_END SET 0
CAN_LIST6_SIZE SET 0
; List Register 7
CAN_LIST7_0 SET 0
CAN_LIST7_BEGIN SET 0
CAN_LIST7_EMPTY SET 0
CAN_LIST7_END SET 0
CAN_LIST7_SIZE SET 0
; MultiCAN Module Control Register
CAN_MCR_0 SET 0
CAN_MCR_0 SET 0
CAN_MCR_MPSEL SET 0
; Module Interrupt Trigger Register
CAN_MITR_IT[31:8] SET 0
CAN_MITR_IT[7:0] SET 0
; CAN Message Object 0 Acceptance Mask Register
CAN_MOAMR0_0 SET 0
CAN_MOAMR0_AM SET 536870911
CAN_MOAMR0_MIDE SET 1
; CAN Message Object 10 Acceptance Mask Register
CAN_MOAMR10_0 SET 0
CAN_MOAMR10_AM SET 536870911
CAN_MOAMR10_MIDE SET 1
; CAN Message Object 11 Acceptance Mask Register
CAN_MOAMR11_0 SET 0
CAN_MOAMR11_AM SET 536870911
CAN_MOAMR11_MIDE SET 1
; CAN Message Object 12 Acceptance Mask Register
CAN_MOAMR12_0 SET 0
CAN_MOAMR12_AM SET 536870911
CAN_MOAMR12_MIDE SET 1
; CAN Message Object 13 Acceptance Mask Register
CAN_MOAMR13_0 SET 0
CAN_MOAMR13_AM SET 536870911
CAN_MOAMR13_MIDE SET 1
; CAN Message Object 14 Acceptance Mask Register
CAN_MOAMR14_0 SET 0
CAN_MOAMR14_AM SET 536870911
CAN_MOAMR14_MIDE SET 1
; CAN Message Object 15 Acceptance Mask Register
CAN_MOAMR15_0 SET 0
CAN_MOAMR15_AM SET 536870911
CAN_MOAMR15_MIDE SET 1
; CAN Message Object 16 Acceptance Mask Register
CAN_MOAMR16_0 SET 0
CAN_MOAMR16_AM SET 536870911
CAN_MOAMR16_MIDE SET 1
; CAN Message Object 17 Acceptance Mask Register
CAN_MOAMR17_0 SET 0
CAN_MOAMR17_AM SET 536870911
CAN_MOAMR17_MIDE SET 1
; CAN Message Object 18 Acceptance Mask Register
CAN_MOAMR18_0 SET 0
CAN_MOAMR18_AM SET 536870911
CAN_MOAMR18_MIDE SET 1
; CAN Message Object 19 Acceptance Mask Register
CAN_MOAMR19_0 SET 0
CAN_MOAMR19_AM SET 536870911
CAN_MOAMR19_MIDE SET 1
; CAN Message Object 1 Acceptance Mask Register
CAN_MOAMR1_0 SET 0
CAN_MOAMR1_AM SET 536870911
CAN_MOAMR1_MIDE SET 1
; CAN Message Object 20 Acceptance Mask Register
CAN_MOAMR20_0 SET 0
CAN_MOAMR20_AM SET 536870911
CAN_MOAMR20_MIDE SET 1
; CAN Message Object 21 Acceptance Mask Register
CAN_MOAMR21_0 SET 0
CAN_MOAMR21_AM SET 536870911
CAN_MOAMR21_MIDE SET 1
; CAN Message Object 22 Acceptance Mask Register
CAN_MOAMR22_0 SET 0
CAN_MOAMR22_AM SET 536870911
CAN_MOAMR22_MIDE SET 1
; CAN Message Object 23 Acceptance Mask Register
CAN_MOAMR23_0 SET 0
CAN_MOAMR23_AM SET 536870911
CAN_MOAMR23_MIDE SET 1
; CAN Message Object 24 Acceptance Mask Register
CAN_MOAMR24_0 SET 0
CAN_MOAMR24_AM SET 536870911
CAN_MOAMR24_MIDE SET 1
; CAN Message Object 25 Acceptance Mask Register
CAN_MOAMR25_0 SET 0
CAN_MOAMR25_AM SET 536870911
CAN_MOAMR25_MIDE SET 1
; CAN Message Object 26 Acceptance Mask Register
CAN_MOAMR26_0 SET 0
CAN_MOAMR26_AM SET 536870911
CAN_MOAMR26_MIDE SET 1
; CAN Message Object 27 Acceptance Mask Register
CAN_MOAMR27_0 SET 0
CAN_MOAMR27_AM SET 536870911
CAN_MOAMR27_MIDE SET 1
; CAN Message Object 28 Acceptance Mask Register
CAN_MOAMR28_0 SET 0
CAN_MOAMR28_AM SET 536870911
CAN_MOAMR28_MIDE SET 1
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