📄 mod_judge.asm

📁 dsp320lf2407上的相关程序文件
💻 ASM
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	LAR	AR3,* ,AR3
	LACK	0
	SACL	* ,AR2
	LAC	* 
	ADDK	1
	SACL	* 
	ZALS	* 
	SUBK	20
	BLZ	L1
L2:
	.line	6
;>>>> 		crc_len=0;
	LACK	0
	LDPK	_crc_len
	SACL	_crc_len
	.line	7
;>>>> 		i_d=0;
	LDPK	_i_d
	SACL	_i_d
EPI0_1:
	.line	8
	MAR	* ,AR1
	SBRK	3
	LAR	AR0,*-
	PSHD	*
	RET

	.endfunc	140,000000000H,2

	.sym	_rec_judge,_rec_judge,32,2,0
	.globl	_rec_judge

	.func	143
;>>>> 	void rec_judge(void)
;>>>> 		unsigned int i;
;>>>> 		switch(step)
;>>>> 			case 0:	
******************************************************
* FUNCTION DEF : _rec_judge
******************************************************
_rec_judge:
	POPD	*+
	SAR	AR0,*+
	SAR	AR1,*
	LARK	AR0,2
	LAR	AR0,*0+

	.sym	_i,1,14,1,16
	B	L3
L4:
	.line	8
;>>>> 				if((data_rec[i_d]&0x00ff)==0x0001)
	LDPK	_i_d
	LAC	_i_d
	ADLK	_data_rec+0,0
	MAR	* ,AR0
	SACL	* 
	LAR	AR3,* ,AR3
	LACK	255
	AND	* ,AR1
	SACL	* 
	SSXM
	LAC	* 
	SUBK	1
	BNZ	L5
	.line	10
;>>>> 					step=1;	/*device addr*/
	LACK	1
	LDPK	_step
	SACL	_step
	.line	11
;>>>> 					crc_buf[0]=0x01;
	SACL	_crc_buf
	.line	12
;>>>> 					crc_len=1;
	SACL	_crc_len
	B	L7
L5:
	.line	14
;>>>> 				else	reset_crc(); 
	CALL	_reset_crc
	.line	15
;>>>> 	            break;
;>>>> 			case 1:
;>>>> 				switch(data_rec[i_d]&0x00ff)
;>>>> 					case 0x0003: 		 /*read holding coil*/
	B	L7
L10:
	.line	26
;>>>> 						crc_buf[1]=0x03;
	LACK	3
	LDPK	_crc_buf+1
	SACL	_crc_buf+1
	.line	27
;>>>> 						pre_fun=3;
	SACL	_pre_fun
	.line	28
;>>>> 						break;
;>>>> 					case 0x0006:  			/*Preset Single Register*/
	B	L11
L12:
	.line	32
;>>>> 						crc_buf[1]=0x06;
	LACK	6
	LDPK	_crc_buf+1
	SACL	_crc_buf+1
	.line	33
;>>>> 						pre_fun=6;
	SACL	_pre_fun
	.line	34
;>>>> 						break;
;>>>> 					case 0x0001:  			/*Read Coil Status*/
	B	L11
L13:
	.line	38
;>>>> 						crc_buf[1]=0x01;
	LACK	1
	LDPK	_crc_buf+1
	SACL	_crc_buf+1
	.line	39
;>>>> 						pre_fun=1;
	SACL	_pre_fun
	.line	40
;>>>> 						break;
;>>>> 					case 0x0002: 			/*Read Input Status*/
	B	L11
L14:
	.line	44
;>>>> 						crc_buf[1]=0x02;
	LACK	2
	LDPK	_crc_buf+1
	SACL	_crc_buf+1
	.line	45
;>>>> 						pre_fun=2; 
	SACL	_pre_fun
	.line	46
;>>>> 						break;
;>>>> 					case 0x0004: 			/*Read Input Registers*/
	B	L11
L15:
	.line	50
;>>>> 						crc_buf[1]=0x04;
	LACK	4
	LDPK	_crc_buf+1
	SACL	_crc_buf+1
	.line	51
;>>>> 						pre_fun=4;
	SACL	_pre_fun
	.line	52
;>>>> 						break;
;>>>> 					case 0x0005: 			/*Force Single Coil*/
	B	L11
L16:
	.line	56
;>>>> 						crc_buf[1]=0x05;
	LACK	5
	LDPK	_crc_buf+1
	SACL	_crc_buf+1
	.line	57
;>>>> 						pre_fun=5;
	SACL	_pre_fun
	.line	58
;>>>> 						break;
;>>>> 					default:
	B	L11
L17:
	.line	62
;>>>> 						reset_crc();
	CALL	_reset_crc,AR1
	B	L11
L9:
	.line	22
	LDPK	_i_d
	LAC	_i_d
	ADLK	_data_rec+0,0
	MAR	* ,AR0
	SACL	* 
	LAR	AR3,* ,AR3
	LACK	255
	AND	* ,AR1
	SACL	* 
	SSXM
	LAC	* 
	SUBK	1
	BZ	L13
	SUBK	1
	BZ	L14
	SUBK	1
	BZ	L10
	SUBK	1
	BZ	L15
	SUBK	1
	BZ	L16
	SUBK	1
	BZ	L12
	B	L17
L11:
	.line	65
;>>>> 				crc_len=2;
	LACK	2
	LDPK	_crc_len
	SACL	_crc_len
	.line	66
;>>>> 				step=2;
	SACL	_step
	.line	67
;>>>> 				break;
;>>>> 			case 2:
	B	L7
L18:
	.line	73
;>>>> 				start_addr_h=(data_rec[i_d]&0x00ff);
	LDPK	_i_d
	LAC	_i_d
	ADLK	_data_rec+0,0
	MAR	* ,AR0
	SACL	* 
	LAR	AR3,* ,AR3
	LACK	255
	AND	* 
	LDPK	_start_addr_h
	SACL	_start_addr_h
	.line	74
;>>>> 				crc_buf[2]=start_addr_h;
	BLDD	_start_addr_h,#_crc_buf+2
	.line	75
;>>>> 				crc_len=3;
	LACK	3
	LDPK	_crc_len
	SACL	_crc_len
	.line	76
;>>>> 				step=21;
	LACK	21
	SACL	_step
	.line	77
;>>>> 				break;
;>>>> 			case 21:
	B	L7
L19:
	.line	81
;>>>> 				start_addr_l=(data_rec[i_d]&0x00ff);
	LDPK	_i_d
	LAC	_i_d
	ADLK	_data_rec+0,0
	MAR	* ,AR0
	SACL	* 
	LAR	AR3,* ,AR3
	LACK	255
	AND	* 
	LDPK	_start_addr_l
	SACL	_start_addr_l
	.line	82
;>>>> 				crc_buf[3]=start_addr_l;
	BLDD	_start_addr_l,#_crc_buf+3
	.line	83
;>>>> 				crc_len=4;
	LACK	4
	LDPK	_crc_len
	SACL	_crc_len
	.line	84
;>>>> 				step=22;
	LACK	22
	SACL	_step
	.line	85
;>>>> 				break;
;>>>> 			case 22:
	B	L7
L20:
	.line	89
;>>>> 				n_data_h=(data_rec[i_d]&0x00ff);
	LDPK	_i_d
	LAC	_i_d
	ADLK	_data_rec+0,0
	MAR	* ,AR0
	SACL	* 
	LAR	AR3,* ,AR3
	LACK	255
	AND	* 
	LDPK	_n_data_h
	SACL	_n_data_h
	.line	90
;>>>> 				crc_buf[4]=n_data_h;
	BLDD	_n_data_h,#_crc_buf+4
	.line	91
;>>>> 				crc_len=5;
	LACK	5
	LDPK	_crc_len
	SACL	_crc_len
	.line	92
;>>>> 				step=23;
	LACK	23
	SACL	_step
	.line	93
;>>>> 				break;
;>>>> 			case 23:
	B	L7
L21:
	.line	97
;>>>> 				n_data_l=(data_rec[i_d]&0x00ff);
	LDPK	_i_d
	LAC	_i_d
	ADLK	_data_rec+0,0
	MAR	* ,AR0
	SACL	* 
	LAR	AR3,* ,AR3
	LACK	255
	AND	* 
	LDPK	_n_data_l
	SACL	_n_data_l
	.line	98
;>>>> 				crc_buf[5]=n_data_l;
	BLDD	_n_data_l,#_crc_buf+5
	.line	99
;>>>> 				crc_len=6;
	LACK	6
	LDPK	_crc_len
	SACL	_crc_len
	.line	100
;>>>> 				step=24;
	LACK	24
	SACL	_step
	.line	101
;>>>> 				break;
;>>>> 			case 24:
	B	L7
L22:
	.line	105
;>>>> 				if(data_rec[i_d]==CRC16(crc_buf,6)/0x0100)
	MAR	* ,AR1
	LACK	6
	SACL	*+
	RSXM
	LALK	_crc_buf+0
	SACL	*+
	CALL	_CRC16
	SBRK	2
	MAR	* ,AR0
	SACL	* 
	RSXM
	LAC	* ,7,AR1
	SACH	* ,1,AR0
	LDPK	_i_d
	LAC	_i_d
	ADLK	_data_rec+0,0
	SACL	* 
	LAR	AR3,* ,AR3
	ZALS	* ,AR1
	SUBS	* 
	BNZ	L23
	.line	107
;>>>> 					step=25;
	LACK	25
	LDPK	_step
	SACL	_step
	B	L7
L23:
	.line	109
;>>>> 				else reset_crc();
	CALL	_reset_crc
	.line	110
;>>>> 				break;
;>>>> 			case 25:
	B	L7
L25:
	.line	114
;>>>> 				if(data_rec[i_d]==CRC16(crc_buf,6)%0x0100)
	MAR	* ,AR1
	LACK	6
	SACL	*+
	RSXM
	LALK	_crc_buf+0
	SACL	*+
	CALL	_CRC16
	SBRK	2
	ANDK	255
	SACL	* ,AR0
	LDPK	_i_d
	LAC	_i_d
	ADLK	_data_rec+0,0
	SACL	* 
	LAR	AR3,* ,AR3
	ZALS	* ,AR1
	SUBS	* 
	BNZ	L26
	.line	116
;>>>> 					ok=1;
;>>>> 					switch(pre_fun)
	LACK	1
	LDPK	_ok
	SACL	_ok
	B	L27
L28:
	.line	119
;>>>> 						case 1:{mod_fun=1;break;}
	LACK	1
	LDPK	_mod_fun
	SACL	_mod_fun
	B	L26
L30:
	.line	120
;>>>> 						case 2:{mod_fun=2;break;}
	LACK	2
	LDPK	_mod_fun
	SACL	_mod_fun
	B	L26
L31:
	.line	121
;>>>> 						case 3:{mod_fun=3;break;}
	LACK	3
	LDPK	_mod_fun
	SACL	_mod_fun
	B	L26
L32:
	.line	122
;>>>> 						case 4:{mod_fun=4;break;}
	LACK	4
	LDPK	_mod_fun
	SACL	_mod_fun
	B	L26
L33:
	.line	123
;>>>> 						case 5:{mod_fun=5;break;}
	LACK	5
	LDPK	_mod_fun
	SACL	_mod_fun
	B	L26
L34:
	.line	124
;>>>> 						case 6:{mod_fun=6;break;}
	LACK	6
	LDPK	_mod_fun
	SACL	_mod_fun
	B	L26
L27:
	.line	117
	LDPK	_pre_fun
	ZALS	_pre_fun
	SUBK	1
	BZ	L28
	SUBK	1
	BZ	L30
	SUBK	1
	BZ	L31
	SUBK	1
	BZ	L32
	SUBK	1
	BZ	L33
	SUBK	1
	BZ	L34
L26:
	.line	127
;>>>> 				reset_crc();
	CALL	_reset_crc,AR1
	.line	130
;>>>> 				transaction(); 
	CALL	_transaction
	.line	132
;>>>> 			*SCITXBUF='';	
	LARK	AR3,28761
	LACK	0
	MAR	* ,AR3
	SACL	* 
	.line	133
;>>>> 				break;
	B	L7
L3:
	.line	4
	LDPK	_step
	ZALS	_step
	BZ	L4
	SUBK	1
	BZ	L9
	SUBK	1
	BZ	L18
	SUBK	19
	BZ	L19
	SUBK	1
	BZ	L20
	SUBK	1
	BZ	L21
	SUBK	1
	BZ	L22
	SUBK	1
	BZ	L25
L7:
EPI0_2:
	.line	136
	MAR	* ,AR1
	SBRK	3
	LAR	AR0,*-
	PSHD	*
	RET

	.endfunc	278,000000000H,2

	.sym	_CRC16,_CRC16,45,2,0
	.globl	_CRC16

	.func	288
;>>>> 	unsigned short CRC16(unsigned char *puchMsg, unsigned short usDataLen)
******************************************************
* FUNCTION DEF : _CRC16
******************************************************
_CRC16:

LF3	.set	0

	POPD	*+
	SAR	AR0,*+
	SAR	AR1,*
	LARK	AR0,4
	LAR	AR0,*0+,AR2

	.sym	_puchMsg,-3+LF3,28,9,16
	.sym	_usDataLen,-4+LF3,13,9,16
	.sym	_uIndex,1,14,1,16
	.sym	_uchCRCHi,2,12,1,16
	.sym	_uchCRCLo,3,12,1,16
	.line	2
;>>>> 	    unsigned uIndex ; /* CRC循环中的索引 */ 
	.line	5
;>>>> 	    unsigned char uchCRCHi = 0xFF ; /* 高CRC字节初始化 */
	LACK	255
	LARK	AR2,2
	MAR	*0+
	SACL	*+
	.line	6
;>>>> 		unsigned char uchCRCLo = 0xFF ; /* 低CRC 字节初始化 */
	SACL	* 
	.line	7
;>>>> 		while (usDataLen--) /* 传输消息缓冲区 */
	SBRK	7-LF3
	ZALS	* 
	SUBK	1
	SACL	* 
	ADDK	1
	ANDK	0FFFFh
	BZ	L36
	MAR	*+
L35:
	.line	9
;>>>> 			uIndex = uchCRCHi ^ *puchMsg++ ; /* 计算CRC */
	LAR	AR3,* ,AR3
	LAC	*+,AR2
	SAR	AR3,* 
	ADRK	5-LF3
	XOR	*-
	SACL	* 
	.line	10
;>>>> 			uchCRCHi = uchCRCLo ^ auchCRCHi[uIndex] ;
	LAC	* ,AR0
	ADLK	_auchCRCHi+0,0
	SACL	* 
	LAR	AR3,* ,AR3
	LAC	* ,AR2
	ADRK	2
	XOR	*-
	SACL	*-
	.line	11
;>>>> 			uchCRCLo = auchCRCLo[uIndex] ;
	LAC	* ,AR0
	ADLK	_auchCRCLo+0,0
	SACL	* 
	LAR	AR3,* ,AR3
	LAC	* ,AR2
	ADRK	2
	SACL	* 
	.line	7
	SBRK	7-LF3
	ZALS	* 
	SUBK	1
	SACL	*+
	ADDK	1
	ANDK	0FFFFh
	BNZ	L35
L36:
	.line	13
;>>>> 	return (uchCRCHi << 8 | uchCRCLo) ;
	LARK	AR2,2
	MAR	*0+
	LAC	*+,8
	OR	* 
	ANDK	0FFFFh
EPI0_3:
	.line	14
	MAR	* ,AR1
	SBRK	5
	LAR	AR0,*-
	PSHD	*
	RET

	.endfunc	301,000000000H,4

	.sym	_crc_buf,_crc_buf,60,2,320,,20
	.globl	_crc_buf
*****************************************************
* UNDEFINED REFERENCES                              *
*****************************************************
	.global	_transaction
	.end
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