ops.h

mips cpu 君正4730 4740的 ucosii 源码 包括系统 摄像头 网络 文件系统等等测试

#define __udc_ep5info_init(c,i,a,p) 			\
do { 							\
  REG_UDC_EP5InfR &= ~UDC_EPInfR_MPS_MASK; 		\
  REG_UDC_EP5InfR |= ((p) << UDC_EPInfR_MPS_BIT); 	\
  REG_UDC_EP5InfR &= ~UDC_EPInfR_ALTS_MASK; 		\
  REG_UDC_EP5InfR |= ((a) << UDC_EPInfR_ALTS_BIT); 	\
  REG_UDC_EP5InfR &= ~UDC_EPInfR_IFN_MASK; 		\
  REG_UDC_EP5InfR |= ((i) << UDC_EPInfR_IFN_BIT); 	\
  REG_UDC_EP5InfR &= ~UDC_EPInfR_CGN_MASK; 		\
  REG_UDC_EP5InfR |= ((c) << UDC_EPInfR_CGN_BIT); 	\
  REG_UDC_EP5InfR &= ~UDC_EPInfR_EPT_MASK; 		\
  REG_UDC_EP5InfR |= UDC_EPInfR_EPT_BULK; 		\
  REG_UDC_EP5InfR &= ~UDC_EPInfR_EPD; 			\
  REG_UDC_EP5InfR |= UDC_EPInfR_EPD_OUT; 		\
  REG_UDC_EP5InfR &= ~UDC_EPInfR_EPN_MASK;		\
  REG_UDC_EP5InfR |= (5 << UDC_EPInfR_EPN_BIT);		\
} while (0)

#define __udc_ep6info_init(c,i,a,p) 			\
do { 							\
  REG_UDC_EP6InfR &= ~UDC_EPInfR_MPS_MASK; 		\
  REG_UDC_EP6InfR |= ((p) << UDC_EPInfR_MPS_BIT); 	\
  REG_UDC_EP6InfR &= ~UDC_EPInfR_ALTS_MASK; 		\
  REG_UDC_EP6InfR |= ((a) << UDC_EPInfR_ALTS_BIT); 	\
  REG_UDC_EP6InfR &= ~UDC_EPInfR_IFN_MASK; 		\
  REG_UDC_EP6InfR |= ((i) << UDC_EPInfR_IFN_BIT); 	\
  REG_UDC_EP6InfR &= ~UDC_EPInfR_CGN_MASK; 		\
  REG_UDC_EP6InfR |= ((c) << UDC_EPInfR_CGN_BIT); 	\
  REG_UDC_EP6InfR &= ~UDC_EPInfR_EPT_MASK; 		\
  REG_UDC_EP6InfR |= UDC_EPInfR_EPT_BULK; 		\
  REG_UDC_EP6InfR &= ~UDC_EPInfR_EPD; 			\
  REG_UDC_EP6InfR |= UDC_EPInfR_EPD_OUT; 		\
  REG_UDC_EP6InfR &= ~UDC_EPInfR_EPN_MASK;		\
  REG_UDC_EP6InfR |= (6 << UDC_EPInfR_EPN_BIT);		\
} while (0)

#define __udc_ep7info_init(c,i,a,p) 			\
do { 							\
  REG_UDC_EP7InfR &= ~UDC_EPInfR_MPS_MASK; 		\
  REG_UDC_EP7InfR |= ((p) << UDC_EPInfR_MPS_BIT); 	\
  REG_UDC_EP7InfR &= ~UDC_EPInfR_ALTS_MASK; 		\
  REG_UDC_EP7InfR |= ((a) << UDC_EPInfR_ALTS_BIT); 	\
  REG_UDC_EP7InfR &= ~UDC_EPInfR_IFN_MASK; 		\
  REG_UDC_EP7InfR |= ((i) << UDC_EPInfR_IFN_BIT); 	\
  REG_UDC_EP7InfR &= ~UDC_EPInfR_CGN_MASK; 		\
  REG_UDC_EP7InfR |= ((c) << UDC_EPInfR_CGN_BIT); 	\
  REG_UDC_EP7InfR &= ~UDC_EPInfR_EPT_MASK; 		\
  REG_UDC_EP7InfR |= UDC_EPInfR_EPT_ISO; 		\
  REG_UDC_EP7InfR &= ~UDC_EPInfR_EPD; 			\
  REG_UDC_EP7InfR |= UDC_EPInfR_EPD_OUT; 		\
  REG_UDC_EP7InfR &= ~UDC_EPInfR_EPN_MASK;		\
  REG_UDC_EP7InfR |= (7 << UDC_EPInfR_EPN_BIT);		\
} while (0)


/***************************************************************************
 * DMAC
 ***************************************************************************/

/* n is the DMA channel (0 - 7) */

#define __dmac_enable_all_channels() \
  ( REG_DMAC_DMACR |= DMAC_DMACR_DME | DMAC_DMACR_PR_ROUNDROBIN )
#define __dmac_disable_all_channels() \
  ( REG_DMAC_DMACR &= ~DMAC_DMACR_DME )

/* p=0,1,2,3 */
#define __dmac_set_priority(p) 				\
do {							\
	REG_DMAC_DMACR &= ~DMAC_DMACR_PR_MASK;		\
	REG_DMAC_DMACR |= ((p) << DMAC_DMACR_PR_BIT);	\
} while (0)

#define __dmac_test_halt_error() ( REG_DMAC_DMACR & DMAC_DMACR_HTR )
#define __dmac_test_addr_error() ( REG_DMAC_DMACR & DMAC_DMACR_AER )

#define __dmac_enable_channel(n) \
  ( REG_DMAC_DCCSR(n) |= DMAC_DCCSR_CHDE )
#define __dmac_disable_channel(n) \
  ( REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_CHDE )
#define __dmac_channel_enabled(n) \
  ( REG_DMAC_DCCSR(n) & DMAC_DCCSR_CHDE )

#define __dmac_channel_enable_irq(n) \
  ( REG_DMAC_DCCSR(n) |= DMAC_DCCSR_TCIE )
#define __dmac_channel_disable_irq(n) \
  ( REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_TCIE )

#define __dmac_channel_transmit_halt_detected(n) \
  (  REG_DMAC_DCCSR(n) & DMAC_DCCSR_HLT )
#define __dmac_channel_transmit_end_detected(n) \
  (  REG_DMAC_DCCSR(n) & DMAC_DCCSR_TC )
#define __dmac_channel_address_error_detected(n) \
  (  REG_DMAC_DCCSR(n) & DMAC_DCCSR_AR )

#define __dmac_channel_clear_transmit_halt(n) \
  (  REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_HLT )
#define __dmac_channel_clear_transmit_end(n) \
  (  REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_TC )
#define __dmac_channel_clear_address_error(n) \
  (  REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_AR )

#define __dmac_channel_set_single_mode(n) \
  (  REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_TM )
#define __dmac_channel_set_block_mode(n) \
  (  REG_DMAC_DCCSR(n) |= DMAC_DCCSR_TM )

#define __dmac_channel_set_transfer_unit_32bit(n)	\
do {							\
	REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_DS_MASK;	\
	REG_DMAC_DCCSR(n) |= DMAC_DCCSR_DS_32b;		\
} while (0)

#define __dmac_channel_set_transfer_unit_16bit(n)	\
do {							\
	REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_DS_MASK;	\
	REG_DMAC_DCCSR(n) |= DMAC_DCCSR_DS_16b;		\
} while (0)

#define __dmac_channel_set_transfer_unit_8bit(n)	\
do {							\
	REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_DS_MASK;	\
	REG_DMAC_DCCSR(n) |= DMAC_DCCSR_DS_8b;		\
} while (0)

#define __dmac_channel_set_transfer_unit_16byte(n)	\
do {							\
	REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_DS_MASK;	\
	REG_DMAC_DCCSR(n) |= DMAC_DCCSR_DS_16B;		\
} while (0)

#define __dmac_channel_set_transfer_unit_32byte(n)	\
do {							\
	REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_DS_MASK;	\
	REG_DMAC_DCCSR(n) |= DMAC_DCCSR_DS_32B;		\
} while (0)

/* w=8,16,32 */
#define __dmac_channel_set_dest_port_width(n,w)		\
do {							\
	REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_DWDH_MASK;	\
	REG_DMAC_DCCSR(n) |= DMAC_DCCSR_DWDH_##w;	\
} while (0)

/* w=8,16,32 */
#define __dmac_channel_set_src_port_width(n,w)		\
do {							\
	REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_SWDH_MASK;	\
	REG_DMAC_DCCSR(n) |= DMAC_DCCSR_SWDH_##w;	\
} while (0)

/* v=0-15 */
#define __dmac_channel_set_rdil(n,v)				\
do {								\
	REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_RDIL_MASK;		\
	REG_DMAC_DCCSR(n) |= ((v) << DMAC_DCCSR_RDIL_BIT);	\
} while (0)

#define __dmac_channel_dest_addr_fixed(n) \
  (  REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_DAM )
#define __dmac_channel_dest_addr_increment(n) \
  (  REG_DMAC_DCCSR(n) |= DMAC_DCCSR_DAM )

#define __dmac_channel_src_addr_fixed(n) \
  (  REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_SAM )
#define __dmac_channel_src_addr_increment(n) \
  (  REG_DMAC_DCCSR(n) |= DMAC_DCCSR_SAM )

#define __dmac_channel_set_eop_high(n) \
  (  REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_EOPM )
#define __dmac_channel_set_eop_low(n) \
  (  REG_DMAC_DCCSR(n) |= DMAC_DCCSR_EOPM )

#define __dmac_channel_set_erdm(n,m)				\
do {								\
	REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_SWDH_MASK;		\
	REG_DMAC_DCCSR(n) |= ((m) << DMAC_DCCSR_ERDM_BIT);	\
} while (0)

#define __dmac_channel_set_eackm(n) \
  ( REG_DMAC_DCCSR(n) |= DMAC_DCCSR_EACKM )
#define __dmac_channel_clear_eackm(n) \
  ( REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_EACKM )

#define __dmac_channel_set_eacks(n) \
  ( REG_DMAC_DCCSR(n) |= DMAC_DCCSR_EACKS )
#define __dmac_channel_clear_eacks(n) \
  ( REG_DMAC_DCCSR(n) &= ~DMAC_DCCSR_EACKS )


#define __dmac_channel_irq_detected(n) \
  ( REG_DMAC_DCCSR(n) & (DMAC_DCCSR_TC | DMAC_DCCSR_AR) )

static __inline__ int __dmac_get_irq(void)
{
	int i;
	for (i=0;i<NUM_DMA;i++)
		if (__dmac_channel_irq_detected(i))
			return i;
	return -1;
}

/***************************************************************************
 * AIC (AC'97 & I2S Controller)
 ***************************************************************************/

#define __aic_enable()		( REG_AIC_FR |= AIC_FR_ENB )
#define __aic_disable()		( REG_AIC_FR &= ~AIC_FR_ENB )
#define __aic_reset()		( REG_AIC_FR |= AIC_FR_RST )
#define __aic_select_ac97()	( REG_AIC_FR &= ~AIC_FR_AUSEL )
#define __aic_select_i2s()	( REG_AIC_FR |= AIC_FR_AUSEL )

#define __i2s_as_master()	( REG_AIC_FR |= AIC_FR_BCKD | AIC_FR_SYNCD )
#define __i2s_as_slave()	( REG_AIC_FR &= ~(AIC_FR_BCKD | AIC_FR_SYNCD) )

#define __aic_set_transmit_trigger(n) 			\
do {							\
	REG_AIC_FR &= ~AIC_FR_TFTH_MASK;		\
	REG_AIC_FR |= ((n) << AIC_FR_TFTH_BIT);		\
} while(0)

#define __aic_set_receive_trigger(n) 			\
do {							\
	REG_AIC_FR &= ~AIC_FR_RFTH_MASK;		\
	REG_AIC_FR |= ((n) << AIC_FR_RFTH_BIT);		\
} while(0)

#define __aic_enable_record()	( REG_AIC_CR |= AIC_CR_EREC )
#define __aic_disable_record()	( REG_AIC_CR &= ~AIC_CR_EREC )
#define __aic_enable_replay()	( REG_AIC_CR |= AIC_CR_ERPL )
#define __aic_disable_replay()	( REG_AIC_CR &= ~AIC_CR_ERPL )
#define __aic_enable_loopback()	( REG_AIC_CR |= AIC_CR_ENLBF )
#define __aic_disable_loopback() ( REG_AIC_CR &= ~AIC_CR_ENLBF )

#define __aic_flush_fifo()	( REG_AIC_CR |= AIC_CR_FLUSH )
#define __aic_unflush_fifo()	( REG_AIC_CR &= ~AIC_CR_FLUSH )

#define __aic_enable_transmit_intr() \
  ( REG_AIC_CR |= (AIC_CR_ETFS | AIC_CR_ETUR) )
#define __aic_disable_transmit_intr() \
  ( REG_AIC_CR &= ~(AIC_CR_ETFS | AIC_CR_ETUR) )
#define __aic_enable_receive_intr() \
  ( REG_AIC_CR |= (AIC_CR_ERFS | AIC_CR_EROR) )
#define __aic_disable_receive_intr() \
  ( REG_AIC_CR &= ~(AIC_CR_ERFS | AIC_CR_EROR) )

#define __aic_enable_transmit_dma()  ( REG_AIC_CR |= AIC_CR_TDMS )
#define __aic_disable_transmit_dma() ( REG_AIC_CR &= ~AIC_CR_TDMS )
#define __aic_enable_receive_dma()   ( REG_AIC_CR |= AIC_CR_RDMS )
#define __aic_disable_receive_dma()  ( REG_AIC_CR &= ~AIC_CR_RDMS )

#define __aic_enable_mono2stereo()
#define __aic_disable_mono2stereo()
#define __aic_enable_byteswap()
#define __aic_disable_byteswap()
#define __aic_enable_unsignadj()
#define __aic_disable_unsignadj()

#define AC97_PCM_XS_L_FRONT   	AIC_ACCR1_XS_SLOT3
#define AC97_PCM_XS_R_FRONT   	AIC_ACCR1_XS_SLOT4
#define AC97_PCM_XS_CENTER    	AIC_ACCR1_XS_SLOT6
#define AC97_PCM_XS_L_SURR    	AIC_ACCR1_XS_SLOT7
#define AC97_PCM_XS_R_SURR    	AIC_ACCR1_XS_SLOT8
#define AC97_PCM_XS_LFE       	AIC_ACCR1_XS_SLOT9

#define AC97_PCM_RS_L_FRONT   	AIC_ACCR1_RS_SLOT3
#define AC97_PCM_RS_R_FRONT   	AIC_ACCR1_RS_SLOT4
#define AC97_PCM_RS_CENTER    	AIC_ACCR1_RS_SLOT6
#define AC97_PCM_RS_L_SURR    	AIC_ACCR1_RS_SLOT7
#define AC97_PCM_RS_R_SURR    	AIC_ACCR1_RS_SLOT8
#define AC97_PCM_RS_LFE       	AIC_ACCR1_RS_SLOT9

#define __ac97_set_xs_none()	( REG_AIC_ACCR1 &= ~AIC_ACCR1_XS_MASK )
#define __ac97_set_xs_mono() 						\
do {									\
	REG_AIC_ACCR1 &= ~AIC_ACCR1_XS_MASK;				\
	REG_AIC_ACCR1 |= AC97_PCM_XS_R_FRONT;				\
} while(0)
#define __ac97_set_xs_stereo() 						\
do {									\
	REG_AIC_ACCR1 &= ~AIC_ACCR1_XS_MASK;				\
	REG_AIC_ACCR1 |= AC97_PCM_XS_L_FRONT | AC97_PCM_XS_R_FRONT;	\
} while(0)

/* In fact, only stereo is support now. */ 
#define __ac97_set_rs_none()	( REG_AIC_ACCR1 &= ~AIC_ACCR1_RS_MASK )
#define __ac97_set_rs_mono() 						\
do {									\
	REG_AIC_ACCR1 &= ~AIC_ACCR1_RS_MASK;				\
	REG_AIC_ACCR1 |= AC97_PCM_RS_R_FRONT;				\
} while(0)
#define __ac97_set_rs_stereo() 						\
do {									\
	REG_AIC_ACCR1 &= ~AIC_ACCR1_RS_MASK;				\
	REG_AIC_ACCR1 |= AC97_PCM_RS_L_FRONT | AC97_PCM_RS_R_FRONT;	\
} while(0)

#define __ac97_warm_reset_codec()		\
 do {						\
	REG_AIC_ACCR2 |= AIC_ACCR2_SA;		\
	REG_AIC_ACCR2 |= AIC_ACCR2_SS;		\
	udelay(1);				\
	REG_AIC_ACCR2 &= ~AIC_ACCR2_SS;		\
	REG_AIC_ACCR2 &= ~AIC_ACCR2_SA;		\
 } while (0)

#define Jz_AC97_RESET_BUG 1

#ifndef Jz_AC97_RESET_BUG
#define __ac97_cold_reset_codec()		\
 do {						\
	REG_AIC_ACCR2 |= AIC_ACCR2_SA;		\
	REG_AIC_ACCR2 &= ~AIC_ACCR2_SS;		\
	REG_AIC_ACCR2 |=  AIC_ACCR2_SR;		\
	udelay(1);				\
	REG_AIC_ACCR2 &= ~AIC_ACCR2_SR;		\
	REG_AIC_ACCR2 &= ~AIC_ACCR2_SA;		\
 } while (0)
#else
#define __ac97_cold_reset_codec()		\
 do {						\
        __gpio_as_output(70); /* SDATA_OUT */	\
        __gpio_as_output(71); /* SDATA_IN */	\
        __gpio_as_output(78); /* SYNC */	\
        __gpio_as_output(69); /* RESET# */	\
	__gpio_clear_pin(70);			\
	__gpio_clear_pin(71);			\
	__gpio_clear_pin(78);			\
	__gpio_clear_pin(69);			\
	udelay(10);				\
	__gpio_set_pin(69);			\
	udelay(1);				\
	__gpio_as_ac97();			\
 } while (0)
#endif

/* n=8,16,18,20 */
#define __ac97_set_iass(n) \
 ( REG_AIC_ACCR2 = (REG_AIC_ACCR2 & ~AIC_ACCR2_IASS_MASK) | AIC_ACCR2_IASS_##n##BIT )
#define __ac97_set_oass(n) \
 ( REG_AIC_ACCR2 = (REG_AIC_ACCR2 & ~AIC_ACCR2_OASS_MASK) | AIC_ACCR2_OASS_##n##BIT )

#define __i2s_select_i2s()            ( REG_AIC_I2SCR &= ~AIC_I2SCR_AMSL )
#define __i2s_select_left_justified() ( REG_AIC_I2SCR |= AIC_I2SCR_AMSL )

/* n=8,16,18,20,24 */
#define __i2s_set_sample_size(n) \
 ( REG_AIC_I2SCR |= (REG_AIC_I2SCR & ~AIC_I2SCR_WL_MASK) | AIC_I2SCR_WL_##n##BIT )

#define __i2s_stop_clock()   ( REG_AIC_I2SCR |= AIC_I2SCR_STPBK )
#define __i2s_start_clock()  ( REG_AIC_I2SCR &= ~AIC_I2SCR_STPBK )

#define __aic_transmit_request()  ( REG_AIC_SR & AIC_SR_TFS )
#define __aic_receive_request()   ( REG_AIC_SR & AIC_SR_RFS )
#define __aic_transmit_underrun() ( REG_AIC_SR & AIC_SR_TUR )
#define __aic_receive_overrun()   ( REG_AIC_SR & AIC_SR_ROR )

#define __aic_clear_errors()      ( REG_AIC_SR &= ~(AIC_SR_TUR | AIC_SR_ROR) )

#define __