📄 ops.h
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#ifndef __OPS_H__#define __OPS_H__/*************************************************************************** * MSC ***************************************************************************/#define __msc_start_op() \ ( REG_MSC_STRPCL = MSC_STRPCL_START_OP | MSC_STRPCL_CLOCK_CONTROL_START )#define __msc_set_resto(to) ( REG_MSC_RESTO = to )#define __msc_set_rdto(to) ( REG_MSC_RDTO = to )#define __msc_set_cmd(cmd) ( REG_MSC_CMD = cmd )#define __msc_set_arg(arg) ( REG_MSC_ARG = arg )#define __msc_set_nob(nob) ( REG_MSC_NOB = nob )#define __msc_get_nob() ( REG_MSC_NOB )#define __msc_set_blklen(len) ( REG_MSC_BLKLEN = len )#define __msc_set_cmdat(cmdat) ( REG_MSC_CMDAT = cmdat )#define __msc_set_cmdat_ioabort() ( REG_MSC_CMDAT |= MSC_CMDAT_IO_ABORT )#define __msc_clear_cmdat_ioabort() ( REG_MSC_CMDAT &= ~MSC_CMDAT_IO_ABORT )#define __msc_set_cmdat_bus_width1() \do { \ REG_MSC_CMDAT &= ~MSC_CMDAT_BUS_WIDTH_MASK; \ REG_MSC_CMDAT |= MSC_CMDAT_BUS_WIDTH_1BIT; \} while(0)#define __msc_set_cmdat_bus_width4() \do { \ REG_MSC_CMDAT &= ~MSC_CMDAT_BUS_WIDTH_MASK; \ REG_MSC_CMDAT |= MSC_CMDAT_BUS_WIDTH_4BIT; \} while(0)#define __msc_set_cmdat_dma_en() ( REG_MSC_CMDAT |= MSC_CMDAT_DMA_EN )#define __msc_set_cmdat_init() ( REG_MSC_CMDAT |= MSC_CMDAT_INIT )#define __msc_set_cmdat_busy() ( REG_MSC_CMDAT |= MSC_CMDAT_BUSY )#define __msc_set_cmdat_stream() ( REG_MSC_CMDAT |= MSC_CMDAT_STREAM_BLOCK )#define __msc_set_cmdat_block() ( REG_MSC_CMDAT &= ~MSC_CMDAT_STREAM_BLOCK )#define __msc_set_cmdat_read() ( REG_MSC_CMDAT &= ~MSC_CMDAT_WRITE_READ )#define __msc_set_cmdat_write() ( REG_MSC_CMDAT |= MSC_CMDAT_WRITE_READ )#define __msc_set_cmdat_data_en() ( REG_MSC_CMDAT |= MSC_CMDAT_DATA_EN )/* r is MSC_CMDAT_RESPONSE_FORMAT_Rx or MSC_CMDAT_RESPONSE_FORMAT_NONE */#define __msc_set_cmdat_res_format(r) \do { \ REG_MSC_CMDAT &= ~MSC_CMDAT_RESPONSE_FORMAT_MASK; \ REG_MSC_CMDAT |= (r); \} while(0)#define __msc_clear_cmdat() \ REG_MSC_CMDAT &= ~( MSC_CMDAT_IO_ABORT | MSC_CMDAT_DMA_EN | MSC_CMDAT_INIT| \ MSC_CMDAT_BUSY | MSC_CMDAT_STREAM_BLOCK | MSC_CMDAT_WRITE_READ | \ MSC_CMDAT_DATA_EN | MSC_CMDAT_RESPONSE_FORMAT_MASK )#define __msc_get_imask() ( REG_MSC_IMASK )#define __msc_mask_all_intrs() ( REG_MSC_IMASK = 0xff )#define __msc_unmask_all_intrs() ( REG_MSC_IMASK = 0x00 )#define __msc_mask_rd() ( REG_MSC_IMASK |= MSC_IMASK_RXFIFO_RD_REQ )#define __msc_unmask_rd() ( REG_MSC_IMASK &= ~MSC_IMASK_RXFIFO_RD_REQ )#define __msc_mask_wr() ( REG_MSC_IMASK |= MSC_IMASK_TXFIFO_WR_REQ )#define __msc_unmask_wr() ( REG_MSC_IMASK &= ~MSC_IMASK_TXFIFO_WR_REQ )#define __msc_mask_endcmdres() ( REG_MSC_IMASK |= MSC_IMASK_END_CMD_RES )#define __msc_unmask_endcmdres() ( REG_MSC_IMASK &= ~MSC_IMASK_END_CMD_RES )#define __msc_mask_datatrandone() ( REG_MSC_IMASK |= MSC_IMASK_DATA_TRAN_DONE )#define __msc_unmask_datatrandone() ( REG_MSC_IMASK &= ~MSC_IMASK_DATA_TRAN_DONE )#define __msc_mask_prgdone() ( REG_MSC_IMASK |= MSC_IMASK_PRG_DONE )#define __msc_unmask_prgdone() ( REG_MSC_IMASK &= ~MSC_IMASK_PRG_DONE )/* n=0,1,2,3,4,5,6,7 */#define __msc_set_clkrt(n) \do { \ REG_MSC_CLKRT = n; \} while(0)#define __msc_get_ireg() ( REG_MSC_IREG )#define __msc_ireg_rd() ( REG_MSC_IREG & MSC_IREG_RXFIFO_RD_REQ )#define __msc_ireg_wr() ( REG_MSC_IREG & MSC_IREG_TXFIFO_WR_REQ )#define __msc_ireg_end_cmd_res() ( REG_MSC_IREG & MSC_IREG_END_CMD_RES )#define __msc_ireg_data_tran_done() ( REG_MSC_IREG & MSC_IREG_DATA_TRAN_DONE )#define __msc_ireg_prg_done() ( REG_MSC_IREG & MSC_IREG_PRG_DONE )#define __msc_ireg_clear_end_cmd_res() ( REG_MSC_IREG = MSC_IREG_END_CMD_RES )#define __msc_ireg_clear_data_tran_done() ( REG_MSC_IREG = MSC_IREG_DATA_TRAN_DONE )#define __msc_ireg_clear_prg_done() ( REG_MSC_IREG = MSC_IREG_PRG_DONE )#define __msc_get_stat() ( REG_MSC_STAT )#define __msc_stat_not_end_cmd_res() ( (REG_MSC_STAT & MSC_STAT_END_CMD_RES) == 0)#define __msc_stat_crc_err() \ ( REG_MSC_STAT & (MSC_STAT_CRC_RES_ERR | MSC_STAT_CRC_READ_ERROR | MSC_STAT_CRC_WRITE_ERROR_YES) )#define __msc_stat_res_crc_err() ( REG_MSC_STAT & MSC_STAT_CRC_RES_ERR )#define __msc_stat_rd_crc_err() ( REG_MSC_STAT & MSC_STAT_CRC_READ_ERROR )#define __msc_stat_wr_crc_err() ( REG_MSC_STAT & MSC_STAT_CRC_WRITE_ERROR_YES )#define __msc_stat_resto_err() ( REG_MSC_STAT & MSC_STAT_TIME_OUT_RES )#define __msc_stat_rdto_err() ( REG_MSC_STAT & MSC_STAT_TIME_OUT_READ )#define __msc_rd_resfifo() ( REG_MSC_RES )#define __msc_rd_rxfifo() ( REG_MSC_RXFIFO )#define __msc_wr_txfifo(v) ( REG_MSC_TXFIFO = v )#define __msc_reset() \do { \ REG_MSC_STRPCL = MSC_STRPCL_RESET; \ while (REG_MSC_STAT & MSC_STAT_IS_RESETTING); \} while (0)#define __msc_start_clk() \do { \ REG_MSC_STRPCL = MSC_STRPCL_CLOCK_CONTROL_START; \} while (0)#define __msc_stop_clk() \do { \ REG_MSC_STRPCL = MSC_STRPCL_CLOCK_CONTROL_STOP; \} while (0)#define MMC_CLK 19169200#define SD_CLK 24576000/* msc_clk should little than pclk and little than clk retrieve from card */#define __msc_calc_clk_divisor(type,dev_clk,msc_clk,lv) \do { \ unsigned int rate, pclk, i; \ pclk = dev_clk; \ rate = type?SD_CLK:MMC_CLK; \ if (msc_clk && msc_clk < pclk) \ pclk = msc_clk; \ i = 0; \ while (pclk < rate) \ { \ i ++; \ rate >>= 1; \ } \ lv = i; \} while(0)/* divide rate to little than or equal to 400kHz */#define __msc_calc_slow_clk_divisor(type, lv) \do { \ unsigned int rate, i; \ rate = (type?SD_CLK:MMC_CLK)/1000/400; \ i = 0; \ while (rate > 0) \ { \ rate >>= 1; \ i ++; \ } \ lv = i; \} while(0)/*************************************************************************** * RTC ***************************************************************************/#define __rtc_start() ( REG_RTC_RCR |= RTC_RCR_START )#define __rtc_stop() ( REG_RTC_RCR &= ~RTC_RCR_START )#define __rtc_enable_alarm() ( REG_RTC_RCR |= RTC_RCR_AE )#define __rtc_disable_alarm() ( REG_RTC_RCR &= ~RTC_RCR_AE )#define __rtc_enable_alarm_irq() ( REG_RTC_RCR |= RTC_RCR_AIE )#define __rtc_disable_alarm_irq() ( REG_RTC_RCR &= ~RTC_RCR_AIE )#define __rtc_enable_1hz_irq() ( REG_RTC_RCR |= RTC_RCR_HZIE )#define __rtc_disable_1hz_irq() ( REG_RTC_RCR &= ~RTC_RCR_HZIE )#define __rtc_is_alarm_flag() ( REG_RTC_RCR & RTC_RCR_AF )#define __rtc_is_1hz_flag() ( REG_RTC_RCR & RTC_RCR_HZ )#define __rtc_clear_alarm_flag() ( REG_RTC_RCR &= ~RTC_RCR_AF )#define __rtc_clear_1hz_flag() ( REG_RTC_RCR &= ~RTC_RCR_HZ )#define __rtc_set_second(s) ( REG_RTC_RSR = (s) )#define __rtc_get_second() REG_RTC_RSR#define __rtc_set_alarm(s) ( REG_RTC_RSAR = (s) )#define __rtc_get_alarm() REG_RTC_RSAR#define __rtc_adjust_1hz(f32k) \ ( REG_RTC_RGR = (REG_RTC_RGR & ~(RTC_REG_DIV_MASK | RTC_RGR_ADJ_MASK)) | f32k | 0 )#define __rtc_lock_1hz() ( REG_RTC_RGR |= RTC_RGR_LOCK )/*************************************************************************** * FIR ***************************************************************************//* enable/disable fir unit */#define __fir_enable() ( REG_FIR_CR1 |= FIR_CR1_FIRUE )#define __fir_disable() ( REG_FIR_CR1 &= ~FIR_CR1_FIRUE )/* enable/disable address comparison */#define __fir_enable_ac() ( REG_FIR_CR1 |= FIR_CR1_ACE )#define __fir_disable_ac() ( REG_FIR_CR1 &= ~FIR_CR1_ACE )/* select frame end mode as underrun or normal */#define __fir_set_eous() ( REG_FIR_CR1 |= FIR_CR1_EOUS )#define __fir_clear_eous() ( REG_FIR_CR1 &= ~FIR_CR1_EOUS )/* enable/disable transmitter idle interrupt */#define __fir_enable_tii() ( REG_FIR_CR1 |= FIR_CR1_TIIE )#define __fir_disable_tii() ( REG_FIR_CR1 &= ~FIR_CR1_TIIE )/* enable/disable transmit FIFO service request interrupt */#define __fir_enable_tfi() ( REG_FIR_CR1 |= FIR_CR1_TFIE )#define __fir_disable_tfi() ( REG_FIR_CR1 &= ~FIR_CR1_TFIE )/* enable/disable receive FIFO service request interrupt */#define __fir_enable_rfi() ( REG_FIR_CR1 |= FIR_CR1_RFIE )#define __fir_disable_rfi() ( REG_FIR_CR1 &= ~FIR_CR1_RFIE )/* enable/disable tx function */#define __fir_tx_enable() ( REG_FIR_CR1 |= FIR_CR1_TXE )#define __fir_tx_disable() ( REG_FIR_CR1 &= ~FIR_CR1_TXE )/* enable/disable rx function */#define __fir_rx_enable() ( REG_FIR_CR1 |= FIR_CR1_RXE )#define __fir_rx_disable() ( REG_FIR_CR1 &= ~FIR_CR1_RXE )/* enable/disable serial infrared interaction pulse (SIP) */#define __fir_enable_sip() ( REG_FIR_CR2 |= FIR_CR2_SIPE )#define __fir_disable_sip() ( REG_FIR_CR2 &= ~FIR_CR2_SIPE )/* un-inverted CRC value is sent out */#define __fir_enable_bcrc() ( REG_FIR_CR2 |= FIR_CR2_BCRC )/* inverted CRC value is sent out */#define __fir_disable_bcrc() ( REG_FIR_CR2 &= ~FIR_CR2_BCRC )/* enable/disable Transmit Frame Length Register */#define __fir_enable_tflr() ( REG_FIR_CR2 |= FIR_CR2_TFLRS )#define __fir_disable_tflr() ( REG_FIR_CR2 &= ~FIR_CR2_TFLRS )/* Preamble is transmitted in idle state */#define __fir_set_iss() ( REG_FIR_CR2 |= FIR_CR2_ISS )/* Abort symbol is transmitted in idle state */#define __fir_clear_iss() ( REG_FIR_CR2 &= ~FIR_CR2_ISS )/* enable/disable loopback mode */#define __fir_enable_loopback() ( REG_FIR_CR2 |= FIR_CR2_LMS )#define __fir_disable_loopback() ( REG_FIR_CR2 &= ~FIR_CR2_LMS )/* select transmit pin polarity */#define __fir_tpp_negative() ( REG_FIR_CR2 |= FIR_CR2_TPPS )#define __fir_tpp_positive() ( REG_FIR_CR2 &= ~FIR_CR2_TPPS )/* select receive pin polarity */#define __fir_rpp_negative() ( REG_FIR_CR2 |= FIR_CR2_RPPS )#define __fir_rpp_positive() ( REG_FIR_CR2 &= ~FIR_CR2_RPPS )/* n=16,32,64,128 */#define __fir_set_txfifo_trigger(n) \do { \ REG_FIR_CR2 &= ~FIR_CR2_TTRG_MASK; \ REG_FIR_CR2 |= FIR_CR2_TTRG_##n; \} while (0)/* n=16,32,64,128 */#define __fir_set_rxfifo_trigger(n) \do { \ REG_FIR_CR2 &= ~FIR_CR2_RTRG_MASK; \ REG_FIR_CR2 |= FIR_CR2_RTRG_##n; \} while (0)/* FIR status checking */#define __fir_test_rfw() ( REG_FIR_SR & FIR_SR_RFW )#define __fir_test_rfa() ( REG_FIR_SR & FIR_SR_RFA )#define __fir_test_tfrtl() ( REG_FIR_SR & FIR_SR_TFRTL )#define __fir_test_rfrtl() ( REG_FIR_SR & FIR_SR_RFRTL )#define __fir_test_urun() ( REG_FIR_SR & FIR_SR_URUN )#define __fir_test_rfte() ( REG_FIR_SR & FIR_SR_RFTE )#define __fir_test_orun() ( REG_FIR_SR & FIR_SR_ORUN )#define __fir_test_crce() ( REG_FIR_SR & FIR_SR_CRCE )#define __fir_test_fend() ( REG_FIR_SR & FIR_SR_FEND )#define __fir_test_tff() ( REG_FIR_SR & FIR_SR_TFF )#define __fir_test_rfe() ( REG_FIR_SR & FIR_SR_RFE )#define __fir_test_tidle() ( REG_FIR_SR & FIR_SR_TIDLE )#define __fir_test_rb() ( REG_FIR_SR & FIR_SR_RB )#define __fir_clear_status() \do { \ REG_FIR_SR |= FIR_SR_RFW | FIR_SR_RFA | FIR_SR_URUN; \} while (0)#define __fir_clear_rfw() ( REG_FIR_SR |= FIR_SR_RFW )#define __fir_clear_rfa() ( REG_FIR_SR |= FIR_SR_RFA )#define __fir_clear_urun() ( REG_FIR_SR |= FIR_SR_URUN )#define __fir_set_tflr(len) \do { \ REG_FIR_TFLR = len; \} while (0)#define __fir_set_addr(a) ( REG_FIR_AR = (a) )#define __fir_write_data(data) ( REG_FIR_TDR = data )#define __fir_read_data(data) ( data = REG_FIR_RDR )/*************************************************************************** * SCC ***************************************************************************/#define __scc_enable(base) ( REG_SCC_CR(base) |= SCC_CR_SCCE )#define __scc_disable(base) ( REG_SCC_CR(base) &= ~SCC_CR_SCCE )#define __scc_set_tx_mode(base) ( REG_SCC_CR(base) |= SCC_CR_TRS )#define __scc_set_rx_mode(base) ( REG_SCC_CR(base) &= ~SCC_CR_TRS )#define __scc_enable_t2r(base) ( REG_SCC_CR(base) |= SCC_CR_T2R )#define __scc_disable_t2r(base) ( REG_SCC_CR(base) &= ~SCC_CR_T2R )#define __scc_clk_as_devclk(base) \do { \ REG_SCC_CR(base) &= ~SCC_CR_FDIV_MASK; \ REG_SCC_CR(base) |= SCC_CR_FDIV_1; \} while (0)#define __scc_clk_as_half_devclk(base) \do { \ REG_SCC_CR(base) &= ~SCC_CR_FDIV_MASK; \ REG_SCC_CR(base) |= SCC_CR_FDIV_2; \} while (0)/* n=1,4,8,14 */#define __scc_set_fifo_trigger(base, n) \do { \ REG_SCC_CR(base) &= ~SCC_CR_TRIG_MASK; \ REG_SCC_CR(base) |= SCC_CR_TRIG_##n; \} while (0)#define __scc_set_protocol(base, p) \do { \ if (p) \ REG_SCC_CR(base) |= SCC_CR_TP; \ else \ REG_SCC_CR(base) &= ~SCC_CR_TP; \} while (0)#define __scc_flush_fifo(base) ( REG_SCC_CR(base) |= SCC_CR_FLUSH )#define __scc_set_invert_mode(base) ( REG_SCC_CR(base) |= SCC_CR_CONV )#define __scc_set_direct_mode(base) ( REG_SCC_CR(base) &= ~SCC_CR_CONV )#define SCC_ERR_INTRS \ ( SCC_CR_ECIE | SCC_CR_EPIE | SCC_CR_RETIE | SCC_CR_EOIE )#define SCC_ALL_INTRS \ ( SCC_CR_TXIE | SCC_CR_RXIE | SCC_CR_TENDIE | SCC_CR_RTOIE | \ SCC_CR_ECIE | SCC_CR_EPIE | SCC_CR_RETIE | SCC_CR_EOIE )#define __scc_enable_err_intrs(base) ( REG_SCC_CR(base) |= SCC_ERR_INTRS )#define __scc_disable_err_intrs(base) ( REG_SCC_CR(base) &= ~SCC_ERR_INTRS )#define SCC_ALL_ERRORS \ ( SCC_SR_ORER | SCC_SR_RTO | SCC_SR_PER | SCC_SR_RETR_3 | SCC_SR_ECNTO)#define __scc_clear_errors(base) ( REG_SCC_SR(base) &= ~SCC_ALL_ERRORS )#define __scc_enable_all_intrs(base) ( REG_SCC_CR(base) |= SCC_ALL_INTRS )#define __scc_disable_all_intrs(base) ( REG_SCC_CR(base) &= ~SCC_ALL_INTRS )#define __scc_enable_tx_intr(base) ( REG_SCC_CR(base) |= SCC_CR_TXIE | SCC_CR_TENDIE )#define __scc_disable_tx_intr(base) ( REG_SCC_CR(base) &= ~(SCC_CR_TXIE | SCC_CR_TENDIE) )⌨️ 快捷键说明
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