📄 jz4730.h
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* HARB *************************************************************************/#define HARB_HAPOR (HARB_BASE + 0x000)#define HARB_HMCTR (HARB_BASE + 0x010)#define HARB_HME8H (HARB_BASE + 0x014)#define HARB_HMCR1 (HARB_BASE + 0x018)#define HARB_HMER2 (HARB_BASE + 0x01C)#define HARB_HMER3 (HARB_BASE + 0x020)#define HARB_HMLTR (HARB_BASE + 0x024)#define REG_HARB_HAPOR REG32(HARB_HAPOR)#define REG_HARB_HMCTR REG32(HARB_HMCTR)#define REG_HARB_HME8H REG32(HARB_HME8H)#define REG_HARB_HMCR1 REG32(HARB_HMCR1)#define REG_HARB_HMER2 REG32(HARB_HMER2)#define REG_HARB_HMER3 REG32(HARB_HMER3)#define REG_HARB_HMLTR REG32(HARB_HMLTR)/* HARB Priority Order Register (HARB_HAPOR) */#define HARB_HAPOR_UCHSEL (1 << 7)#define HARB_HAPOR_PRIO_BIT 0#define HARB_HAPOR_PRIO_MASK (0xf << HARB_HAPOR_PRIO_BIT)/* AHB Monitor Control Register (HARB_HMCTR) */#define HARB_HMCTR_HET3_BIT 20#define HARB_HMCTR_HET3_MASK (0xf << HARB_HMCTR_HET3_BIT)#define HARB_HMCTR_HMS3_BIT 16#define HARB_HMCTR_HMS3_MASK (0xf << HARB_HMCTR_HMS3_BIT)#define HARB_HMCTR_HET2_BIT 12#define HARB_HMCTR_HET2_MASK (0xf << HARB_HMCTR_HET2_BIT)#define HARB_HMCTR_HMS2_BIT 8#define HARB_HMCTR_HMS2_MASK (0xf << HARB_HMCTR_HMS2_BIT)#define HARB_HMCTR_HOVF3 (1 << 7)#define HARB_HMCTR_HOVF2 (1 << 6)#define HARB_HMCTR_HOVF1 (1 << 5)#define HARB_HMCTR_HRST (1 << 4)#define HARB_HMCTR_HEE3 (1 << 2)#define HARB_HMCTR_HEE2 (1 << 1)#define HARB_HMCTR_HEE1 (1 << 0)/* AHB Monitor Event 8bits High Register (HARB_HME8H) */#define HARB_HME8H_HC8H1_BIT 16#define HARB_HME8H_HC8H1_MASK (0xff << HARB_HME8H_HC8H1_BIT)#define HARB_HME8H_HC8H2_BIT 8#define HARB_HME8H_HC8H2_MASK (0xff << HARB_HME8H_HC8H2_BIT)#define HARB_HME8H_HC8H3_BIT 0#define HARB_HME8H_HC8H3_MASK (0xff << HARB_HME8H_HC8H3_BIT)/* AHB Monitor Latency Register (HARB_HMLTR) */#define HARB_HMLTR_HLT2_BIT 16#define HARB_HMLTR_HLT2_MASK (0xffff << HARB_HMLTR_HLT2_BIT)#define HARB_HMLTR_HLT3_BIT 0#define HARB_HMLTR_HLT3_MASK (0xffff << HARB_HMLTR_HLT3_BIT)/************************************************************************* * I2C *************************************************************************/#define I2C_DR (I2C_BASE + 0x000)#define I2C_CR (I2C_BASE + 0x004)#define I2C_SR (I2C_BASE + 0x008)#define I2C_GR (I2C_BASE + 0x00C)#define REG_I2C_DR REG8(I2C_DR)#define REG_I2C_CR REG8(I2C_CR)#define REG_I2C_SR REG8(I2C_SR)#define REG_I2C_GR REG16(I2C_GR)/* I2C Control Register (I2C_CR) */#define I2C_CR_IEN (1 << 4)#define I2C_CR_STA (1 << 3)#define I2C_CR_STO (1 << 2)#define I2C_CR_AC (1 << 1)#define I2C_CR_I2CE (1 << 0)/* I2C Status Register (I2C_SR) */#define I2C_SR_STX (1 << 4)#define I2C_SR_BUSY (1 << 3)#define I2C_SR_TEND (1 << 2)#define I2C_SR_DRF (1 << 1)#define I2C_SR_ACKF (1 << 0)/************************************************************************* * UDC *************************************************************************/#define UDC_EP0InCR (UDC_BASE + 0x00)#define UDC_EP0InSR (UDC_BASE + 0x04)#define UDC_EP0InBSR (UDC_BASE + 0x08)#define UDC_EP0InMPSR (UDC_BASE + 0x0c)#define UDC_EP0InDesR (UDC_BASE + 0x14)#define UDC_EP1InCR (UDC_BASE + 0x20)#define UDC_EP1InSR (UDC_BASE + 0x24)#define UDC_EP1InBSR (UDC_BASE + 0x28)#define UDC_EP1InMPSR (UDC_BASE + 0x2c)#define UDC_EP1InDesR (UDC_BASE + 0x34)#define UDC_EP2InCR (UDC_BASE + 0x40)#define UDC_EP2InSR (UDC_BASE + 0x44)#define UDC_EP2InBSR (UDC_BASE + 0x48)#define UDC_EP2InMPSR (UDC_BASE + 0x4c)#define UDC_EP2InDesR (UDC_BASE + 0x54)#define UDC_EP3InCR (UDC_BASE + 0x60)#define UDC_EP3InSR (UDC_BASE + 0x64)#define UDC_EP3InBSR (UDC_BASE + 0x68)#define UDC_EP3InMPSR (UDC_BASE + 0x6c)#define UDC_EP3InDesR (UDC_BASE + 0x74)#define UDC_EP4InCR (UDC_BASE + 0x80)#define UDC_EP4InSR (UDC_BASE + 0x84)#define UDC_EP4InBSR (UDC_BASE + 0x88)#define UDC_EP4InMPSR (UDC_BASE + 0x8c)#define UDC_EP4InDesR (UDC_BASE + 0x94)#define UDC_EP0OutCR (UDC_BASE + 0x200)#define UDC_EP0OutSR (UDC_BASE + 0x204)#define UDC_EP0OutPFNR (UDC_BASE + 0x208)#define UDC_EP0OutMPSR (UDC_BASE + 0x20c)#define UDC_EP0OutSBPR (UDC_BASE + 0x210)#define UDC_EP0OutDesR (UDC_BASE + 0x214)#define UDC_EP5OutCR (UDC_BASE + 0x2a0)#define UDC_EP5OutSR (UDC_BASE + 0x2a4)#define UDC_EP5OutPFNR (UDC_BASE + 0x2a8)#define UDC_EP5OutMPSR (UDC_BASE + 0x2ac)#define UDC_EP5OutDesR (UDC_BASE + 0x2b4)#define UDC_EP6OutCR (UDC_BASE + 0x2c0)#define UDC_EP6OutSR (UDC_BASE + 0x2c4)#define UDC_EP6OutPFNR (UDC_BASE + 0x2c8)#define UDC_EP6OutMPSR (UDC_BASE + 0x2cc)#define UDC_EP6OutDesR (UDC_BASE + 0x2d4)#define UDC_EP7OutCR (UDC_BASE + 0x2e0)#define UDC_EP7OutSR (UDC_BASE + 0x2e4)#define UDC_EP7OutPFNR (UDC_BASE + 0x2e8)#define UDC_EP7OutMPSR (UDC_BASE + 0x2ec)#define UDC_EP7OutDesR (UDC_BASE + 0x2f4)#define UDC_DevCFGR (UDC_BASE + 0x400)#define UDC_DevCR (UDC_BASE + 0x404)#define UDC_DevSR (UDC_BASE + 0x408)#define UDC_DevIntR (UDC_BASE + 0x40c)#define UDC_DevIntMR (UDC_BASE + 0x410)#define UDC_EPIntR (UDC_BASE + 0x414)#define UDC_EPIntMR (UDC_BASE + 0x418)#define UDC_STCMAR (UDC_BASE + 0x500)#define UDC_EP0InfR (UDC_BASE + 0x504)#define UDC_EP1InfR (UDC_BASE + 0x508)#define UDC_EP2InfR (UDC_BASE + 0x50c)#define UDC_EP3InfR (UDC_BASE + 0x510)#define UDC_EP4InfR (UDC_BASE + 0x514)#define UDC_EP5InfR (UDC_BASE + 0x518)#define UDC_EP6InfR (UDC_BASE + 0x51c)#define UDC_EP7InfR (UDC_BASE + 0x520)#define UDC_TXCONFIRM (UDC_BASE + 0x41C)#define UDC_TXZLP (UDC_BASE + 0x420)#define UDC_RXCONFIRM (UDC_BASE + 0x41C)#define UDC_RXFIFO (UDC_BASE + 0x800)#define UDC_TXFIFOEP0 (UDC_BASE + 0x840)#define REG_UDC_EP0InCR REG32(UDC_EP0InCR)#define REG_UDC_EP0InSR REG32(UDC_EP0InSR)#define REG_UDC_EP0InBSR REG32(UDC_EP0InBSR)#define REG_UDC_EP0InMPSR REG32(UDC_EP0InMPSR)#define REG_UDC_EP0InDesR REG32(UDC_EP0InDesR)#define REG_UDC_EP1InCR REG32(UDC_EP1InCR)#define REG_UDC_EP1InSR REG32(UDC_EP1InSR)#define REG_UDC_EP1InBSR REG32(UDC_EP1InBSR)#define REG_UDC_EP1InMPSR REG32(UDC_EP1InMPSR)#define REG_UDC_EP1InDesR REG32(UDC_EP1InDesR)#define REG_UDC_EP2InCR REG32(UDC_EP2InCR)#define REG_UDC_EP2InSR REG32(UDC_EP2InSR)#define REG_UDC_EP2InBSR REG32(UDC_EP2InBSR)#define REG_UDC_EP2InMPSR REG32(UDC_EP2InMPSR)#define REG_UDC_EP2InDesR REG32(UDC_EP2InDesR)#define REG_UDC_EP3InCR REG32(UDC_EP3InCR)#define REG_UDC_EP3InSR REG32(UDC_EP3InSR)#define REG_UDC_EP3InBSR REG32(UDC_EP3InBSR)#define REG_UDC_EP3InMPSR REG32(UDC_EP3InMPSR)#define REG_UDC_EP3InDesR REG32(UDC_EP3InDesR)#define REG_UDC_EP4InCR REG32(UDC_EP4InCR)#define REG_UDC_EP4InSR REG32(UDC_EP4InSR)#define REG_UDC_EP4InBSR REG32(UDC_EP4InBSR)#define REG_UDC_EP4InMPSR REG32(UDC_EP4InMPSR)#define REG_UDC_EP4InDesR REG32(UDC_EP4InDesR)#define REG_UDC_EP0OutCR REG32(UDC_EP0OutCR)#define REG_UDC_EP0OutSR REG32(UDC_EP0OutSR)#define REG_UDC_EP0OutPFNR REG32(UDC_EP0OutPFNR)#define REG_UDC_EP0OutMPSR REG32(UDC_EP0OutMPSR)#define REG_UDC_EP0OutSBPR REG32(UDC_EP0OutSBPR)#define REG_UDC_EP0OutDesR REG32(UDC_EP0OutDesR)#define REG_UDC_EP5OutCR REG32(UDC_EP5OutCR)#define REG_UDC_EP5OutSR REG32(UDC_EP5OutSR)#define REG_UDC_EP5OutPFNR REG32(UDC_EP5OutPFNR)#define REG_UDC_EP5OutMPSR REG32(UDC_EP5OutMPSR)#define REG_UDC_EP5OutDesR REG32(UDC_EP5OutDesR)#define REG_UDC_EP6OutCR REG32(UDC_EP6OutCR)#define REG_UDC_EP6OutSR REG32(UDC_EP6OutSR)#define REG_UDC_EP6OutPFNR REG32(UDC_EP6OutPFNR)#define REG_UDC_EP6OutMPSR REG32(UDC_EP6OutMPSR)#define REG_UDC_EP6OutDesR REG32(UDC_EP6OutDesR)#define REG_UDC_EP7OutCR REG32(UDC_EP7OutCR)#define REG_UDC_EP7OutSR REG32(UDC_EP7OutSR)#define REG_UDC_EP7OutPFNR REG32(UDC_EP7OutPFNR)#define REG_UDC_EP7OutMPSR REG32(UDC_EP7OutMPSR)#define REG_UDC_EP7OutDesR REG32(UDC_EP7OutDesR)#define REG_UDC_DevCFGR REG32(UDC_DevCFGR)#define REG_UDC_DevCR REG32(UDC_DevCR)#define REG_UDC_DevSR REG32(UDC_DevSR)#define REG_UDC_DevIntR REG32(UDC_DevIntR)#define REG_UDC_DevIntMR REG32(UDC_DevIntMR)#define REG_UDC_EPIntR REG32(UDC_EPIntR)#define REG_UDC_EPIntMR REG32(UDC_EPIntMR)#define REG_UDC_STCMAR REG32(UDC_STCMAR)#define REG_UDC_EP0InfR REG32(UDC_EP0InfR)#define REG_UDC_EP1InfR REG32(UDC_EP1InfR)#define REG_UDC_EP2InfR REG32(UDC_EP2InfR)#define REG_UDC_EP3InfR REG32(UDC_EP3InfR)#define REG_UDC_EP4InfR REG32(UDC_EP4InfR)#define REG_UDC_EP5InfR REG32(UDC_EP5InfR)#define REG_UDC_EP6InfR REG32(UDC_EP6InfR)#define REG_UDC_EP7InfR REG32(UDC_EP7InfR)#define UDC_DevCFGR_PI (1 << 5)#define UDC_DevCFGR_SS (1 << 4)#define UDC_DevCFGR_SP (1 << 3)#define UDC_DevCFGR_RW (1 << 2)#define UDC_DevCFGR_SPD_BIT 0#define UDC_DevCFGR_SPD_MASK (0x03 << UDC_DevCFGR_SPD_BIT) #define UDC_DevCFGR_SPD_HS (0 << UDC_DevCFGR_SPD_BIT) #define UDC_DevCFGR_SPD_LS (2 << UDC_DevCFGR_SPD_BIT) #define UDC_DevCFGR_SPD_FS (3 << UDC_DevCFGR_SPD_BIT)#define UDC_DevCR_DM (1 << 9)#define UDC_DevCR_BE (1 << 5)#define UDC_DevCR_RES (1 << 0)#define UDC_DevSR_ENUMSPD_BIT 13#define UDC_DevSR_ENUMSPD_MASK (0x03 << UDC_DevSR_ENUMSPD_BIT) #define UDC_DevSR_ENUMSPD_HS (0 << UDC_DevSR_ENUMSPD_BIT) #define UDC_DevSR_ENUMSPD_LS (2 << UDC_DevSR_ENUMSPD_BIT) #define UDC_DevSR_ENUMSPD_FS (3 << UDC_DevSR_ENUMSPD_BIT)#define UDC_DevSR_SUSP (1 << 12)#define UDC_DevSR_ALT_BIT 8#define UDC_DevSR_ALT_MASK (0x0f << UDC_DevSR_ALT_BIT)#define UDC_DevSR_INTF_BIT 4#define UDC_DevSR_INTF_MASK (0x0f << UDC_DevSR_INTF_BIT)#define UDC_DevSR_CFG_BIT 0#define UDC_DevSR_CFG_MASK (0x0f << UDC_DevSR_CFG_BIT)#define UDC_DevIntR_ENUM (1 << 6)#define UDC_DevIntR_SOF (1 << 5)#define UDC_DevIntR_US (1 << 4)#define UDC_DevIntR_UR (1 << 3)#define UDC_DevIntR_SI (1 << 1)#define UDC_DevIntR_SC (1 << 0)#define UDC_EPIntR_OUTEP_BIT 16#define UDC_EPIntR_OUTEP_MASK (0xffff << UDC_EPIntR_OUTEP_BIT)#define UDC_EPIntR_OUTEP0 0x00010000#define UDC_EPIntR_OUTEP5 0x00200000#define UDC_EPIntR_OUTEP6 0x00400000#define UDC_EPIntR_OUTEP7 0x00800000#define UDC_EPIntR_INEP_BIT 0#define UDC_EPIntR_INEP_MASK (0xffff << UDC_EPIntR_INEP_BIT)#define UDC_EPIntR_INEP0 0x00000001#define UDC_EPIntR_INEP1 0x00000002#define UDC_EPIntR_INEP2 0x00000004#define UDC_EPIntR_INEP3 0x00000008#define UDC_EPIntR_INEP4 0x00000010#define UDC_EPIntMR_OUTEP_BIT 16#define UDC_EPIntMR_OUTEP_MASK (0xffff << UDC_EPIntMR_OUTEP_BIT)#define UDC_EPIntMR_INEP_BIT 0#define UDC_EPIntMR_INEP_MASK (0xffff << UDC_EPIntMR_INEP_BIT)#define UDC_EPCR_ET_BIT 4#define UDC_EPCR_ET_MASK (0x03 << UDC_EPCR_ET_BIT) #define UDC_EPCR_ET_CTRL (0 << UDC_EPCR_ET_BIT) #define UDC_EPCR_ET_ISO (1 << UDC_EPCR_ET_BIT) #define UDC_EPCR_ET_BULK (2 << UDC_EPCR_ET_BIT) #define UDC_EPCR_ET_INTR (3 << UDC_EPCR_ET_BIT)#define UDC_EPCR_SN (1 << 2)#define UDC_EPCR_F (1 << 1)#define UDC_EPCR_S (1 << 0)#define UDC_EPSR_RXPKTSIZE_BIT 11#define UDC_EPSR_RXPKTSIZE_MASK (0x7ff << UDC_EPSR_RXPKTSIZE_BIT)#define UDC_EPSR_IN (1 << 6)#define UDC_EPSR_OUT_BIT 4#define UDC_EPSR_OUT_MASK (0x03 << UDC_EPSR_OUT_BIT) #define UDC_EPSR_OUT_NONE (0 << UDC_EPSR_OUT_BIT) #define UDC_EPSR_OUT_RCVDATA (1 << UDC_EPSR_OUT_BIT) #define UDC_EPSR_OUT_RCVSETUP (2 << UDC_EPSR_OUT_BIT)#define UDC_EPSR_PID_BIT 0#define UDC_EPSR_PID_MASK (0x0f << UDC_EPSR_PID_BIT)#define UDC_EPInfR_MPS_BIT 19#define UDC_EPInfR_MPS_MASK (0x3ff << UDC_EPInfR_MPS_BIT)#define UDC_EPInfR_ALTS_BIT 15#define UDC_EPInfR_ALTS_MASK (0x0f << UDC_EPInfR_ALTS_BIT)#define UDC_EPInfR_IFN_BIT 11#define UDC_EPInfR_IFN_MASK (0x0f << UDC_EPInfR_IFN_BIT)#define UDC_EPInfR_CGN_BIT 7#define UDC_EPInfR_CGN_MASK (0x0f << UDC_EPInfR_CGN_BIT)#define UDC_EPInfR_EPT_BIT 5#define UDC_EPInfR_EPT_MASK (0x03 << UDC_EPInfR_EPT_BIT) #define UDC_EPInfR_EPT_CTRL (0 << UDC_EPInfR_EPT_BIT) #define UDC_EPInfR_EPT_ISO (1 << UDC_EPInfR_EPT_BIT) #define UDC_EPInfR_EPT_BULK (2 << UDC_EPInfR_EPT_BIT) #define UDC_EPInfR_EPT_INTR (3 << UDC_EPInfR_EPT_BIT)#define UDC_EPInfR_EPD (1 << 4) #define UDC_EPInfR_EPD_OUT (0 << 4) #define UDC_EPInfR_EPD_IN (1 << 4)#define UDC_EPInfR_EPN_BIT 0#define UDC_EPInfR_EPN_MASK (0xf << UDC_EPInfR_EPN_BIT)/************************************************************************* * DMAC *************************************************************************/#define DMAC_DSAR(n) (DMAC_BASE + (0x00 + (n) * 0x20))#define DMAC_DDAR(n) (DMAC_BASE + (0x04 + (n) * 0x20))#define DMAC_DTCR(n) (DMAC_BASE + (0x08 + (n) * 0x20))#define DMAC_DRSR(n) (DMAC_BASE + (0x0c + (n) * 0x20))#define DMAC_DCCSR(n) (DMAC_BASE + (0x10 + (n) * 0x20))#define DMAC_DMAIPR (DMAC_BASE + 0xf8)#define DMAC_DMACR (DMAC_BASE + 0xfc)#define REG_DMAC_DSAR(n) REG32(DMAC_DSAR((n)))#define REG_DMAC_DDAR(n) REG32(DMAC_DDAR((n)))#define REG_DMAC_DTCR(n) REG32(DMAC_DTCR((n)))#define REG_DMAC_DRSR(n) REG32(DMAC_DRSR((n)))#define REG_DMAC_DCCSR(n) REG32(DMAC_DCCSR((n)))#define REG_DMAC_⌨️ 快捷键说明
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