📄 jz4730.h
字号:
#define SCC_CR_EPIE (1 << 8)#define SCC_CR_RETIE (1 << 7)#define SCC_CR_EOIE (1 << 6)#define SCC_CR_TSEND (1 << 3)#define SCC_CR_PX_BIT 1#define SCC_CR_PX_MASK (0x3 << SCC_CR_PX_BIT) #define SCC_CR_PX_NOT_SUPPORT (0 << SCC_CR_PX_BIT) /* SCC does not support clock stop */ #define SCC_CR_PX_STOP_LOW (1 << SCC_CR_PX_BIT) /* SCC_CLK stops at state low */ #define SCC_CR_PX_STOP_HIGH (2 << SCC_CR_PX_BIT) /* SCC_CLK stops at state high */#define SCC_CR_CLKSTP (1 << 0)/* SCC Status Register (SCC_SR) */#define SCC_SR_TRANS (1 << 15)#define SCC_SR_ORER (1 << 12)#define SCC_SR_RTO (1 << 11)#define SCC_SR_PER (1 << 10)#define SCC_SR_TFTG (1 << 9)#define SCC_SR_RFTG (1 << 8)#define SCC_SR_TEND (1 << 7)#define SCC_SR_RETR_3 (1 << 4)#define SCC_SR_ECNTO (1 << 0)/************************************************************************* * ETH *************************************************************************/#define ETH_BMR (ETH_BASE + 0x1000)#define ETH_TPDR (ETH_BASE + 0x1004)#define ETH_RPDR (ETH_BASE + 0x1008)#define ETH_RAR (ETH_BASE + 0x100C)#define ETH_TAR (ETH_BASE + 0x1010)#define ETH_SR (ETH_BASE + 0x1014)#define ETH_CR (ETH_BASE + 0x1018)#define ETH_IER (ETH_BASE + 0x101C)#define ETH_MFCR (ETH_BASE + 0x1020)#define ETH_CTAR (ETH_BASE + 0x1050)#define ETH_CRAR (ETH_BASE + 0x1054)#define ETH_MCR (ETH_BASE + 0x0000)#define ETH_MAHR (ETH_BASE + 0x0004)#define ETH_MALR (ETH_BASE + 0x0008)#define ETH_HTHR (ETH_BASE + 0x000C)#define ETH_HTLR (ETH_BASE + 0x0010)#define ETH_MIAR (ETH_BASE + 0x0014)#define ETH_MIDR (ETH_BASE + 0x0018)#define ETH_FCR (ETH_BASE + 0x001C)#define ETH_VTR1 (ETH_BASE + 0x0020)#define ETH_VTR2 (ETH_BASE + 0x0024)#define ETH_WKFR (ETH_BASE + 0x0028)#define ETH_PMTR (ETH_BASE + 0x002C)#define REG_ETH_BMR REG32(ETH_BMR)#define REG_ETH_TPDR REG32(ETH_TPDR)#define REG_ETH_RPDR REG32(ETH_RPDR)#define REG_ETH_RAR REG32(ETH_RAR)#define REG_ETH_TAR REG32(ETH_TAR)#define REG_ETH_SR REG32(ETH_SR)#define REG_ETH_CR REG32(ETH_CR)#define REG_ETH_IER REG32(ETH_IER)#define REG_ETH_MFCR REG32(ETH_MFCR)#define REG_ETH_CTAR REG32(ETH_CTAR)#define REG_ETH_CRAR REG32(ETH_CRAR)#define REG_ETH_MCR REG32(ETH_MCR)#define REG_ETH_MAHR REG32(ETH_MAHR)#define REG_ETH_MALR REG32(ETH_MALR)#define REG_ETH_HTHR REG32(ETH_HTHR)#define REG_ETH_HTLR REG32(ETH_HTLR)#define REG_ETH_MIAR REG32(ETH_MIAR)#define REG_ETH_MIDR REG32(ETH_MIDR)#define REG_ETH_FCR REG32(ETH_FCR)#define REG_ETH_VTR1 REG32(ETH_VTR1)#define REG_ETH_VTR2 REG32(ETH_VTR2)#define REG_ETH_WKFR REG32(ETH_WKFR)#define REG_ETH_PMTR REG32(ETH_PMTR)/* Bus Mode Register (ETH_BMR) */#define ETH_BMR_DBO (1 << 20)#define ETH_BMR_PBL_BIT 8#define ETH_BMR_PBL_MASK (0x3f << ETH_BMR_PBL_BIT) #define ETH_BMR_PBL_1 (0x1 << ETH_BMR_PBL_BIT) #define ETH_BMR_PBL_4 (0x4 << ETH_BMR_PBL_BIT)#define ETH_BMR_BLE (1 << 7)#define ETH_BMR_DSL_BIT 2#define ETH_BMR_DSL_MASK (0x1f << ETH_BMR_DSL_BIT) #define ETH_BMR_DSL_0 (0x0 << ETH_BMR_DSL_BIT) #define ETH_BMR_DSL_1 (0x1 << ETH_BMR_DSL_BIT) #define ETH_BMR_DSL_2 (0x2 << ETH_BMR_DSL_BIT) #define ETH_BMR_DSL_4 (0x4 << ETH_BMR_DSL_BIT) #define ETH_BMR_DSL_8 (0x8 << ETH_BMR_DSL_BIT)#define ETH_BMR_SWR (1 << 0)/* DMA Status Register (ETH_SR) */#define ETH_SR_EB_BIT 23#define ETH_SR_EB_MASK (0x7 << ETH_SR_EB_BIT) #define ETH_SR_EB_TX_ABORT (0x1 << ETH_SR_EB_BIT) #define ETH_SR_EB_RX_ABORT (0x2 << ETH_SR_EB_BIT)#define ETH_SR_TS_BIT 20#define ETH_SR_TS_MASK (0x7 << ETH_SR_TS_BIT) #define ETH_SR_TS_STOP (0x0 << ETH_SR_TS_BIT) #define ETH_SR_TS_FTD (0x1 << ETH_SR_TS_BIT) #define ETH_SR_TS_WEOT (0x2 << ETH_SR_TS_BIT) #define ETH_SR_TS_QDAT (0x3 << ETH_SR_TS_BIT) #define ETH_SR_TS_SUSPEND (0x6 << ETH_SR_TS_BIT) #define ETH_SR_TS_CTD (0x7 << ETH_SR_TS_BIT)#define ETH_SR_RS_BIT 17#define ETH_SR_RS_MASK (0x7 << ETH_SR_RS_BIT) #define ETH_SR_RS_STOP (0x0 << ETH_SR_RS_BIT) #define ETH_SR_RS_FRD (0x1 << ETH_SR_RS_BIT) #define ETH_SR_RS_CEOR (0x2 << ETH_SR_RS_BIT) #define ETH_SR_RS_WRP (0x3 << ETH_SR_RS_BIT) #define ETH_SR_RS_SUSPEND (0x4 << ETH_SR_RS_BIT) #define ETH_SR_RS_CRD (0x5 << ETH_SR_RS_BIT) #define ETH_SR_RS_FCF (0x6 << ETH_SR_RS_BIT) #define ETH_SR_RS_QRF (0x7 << ETH_SR_RS_BIT)#define ETH_SR_NIS (1 << 16)#define ETH_SR_AIS (1 << 15)#define ETH_SR_ERI (1 << 14)#define ETH_SR_FBE (1 << 13)#define ETH_SR_ETI (1 << 10)#define ETH_SR_RWT (1 << 9)#define ETH_SR_RPS (1 << 8)#define ETH_SR_RU (1 << 7)#define ETH_SR_RI (1 << 6)#define ETH_SR_UNF (1 << 5)#define ETH_SR_TJT (1 << 3)#define ETH_SR_TU (1 << 2)#define ETH_SR_TPS (1 << 1)#define ETH_SR_TI (1 << 0)/* Control (Operation Mode) Register (ETH_CR) */#define ETH_CR_TTM (1 << 22)#define ETH_CR_SF (1 << 21)#define ETH_CR_TR_BIT 14#define ETH_CR_TR_MASK (0x3 << ETH_CR_TR_BIT)#define ETH_CR_ST (1 << 13)#define ETH_CR_OSF (1 << 2)#define ETH_CR_SR (1 << 1)/* Interrupt Enable Register (ETH_IER) */#define ETH_IER_NI (1 << 16)#define ETH_IER_AI (1 << 15)#define ETH_IER_ERE (1 << 14)#define ETH_IER_FBE (1 << 13)#define ETH_IER_ET (1 << 10)#define ETH_IER_RWE (1 << 9)#define ETH_IER_RS (1 << 8)#define ETH_IER_RU (1 << 7)#define ETH_IER_RI (1 << 6)#define ETH_IER_UN (1 << 5)#define ETH_IER_TJ (1 << 3)#define ETH_IER_TU (1 << 2)#define ETH_IER_TS (1 << 1)#define ETH_IER_TI (1 << 0)/* Missed Frame and Buffer Overflow Counter Register (ETH_MFCR) */#define ETH_MFCR_OVERFLOW_BIT 17#define ETH_MFCR_OVERFLOW_MASK (0x7ff << ETH_MFCR_OVERFLOW_BIT)#define ETH_MFCR_MFC_BIT 0#define ETH_MFCR_MFC_MASK (0xffff << ETH_MFCR_MFC_BIT)/* MAC Control Register (ETH_MCR) */#define ETH_MCR_RA (1 << 31)#define ETH_MCR_HBD (1 << 28)#define ETH_MCR_PS (1 << 27)#define ETH_MCR_DRO (1 << 23)#define ETH_MCR_OM_BIT 21#define ETH_MCR_OM_MASK (0x3 << ETH_MCR_OM_BIT) #define ETH_MCR_OM_NORMAL (0x0 << ETH_MCR_OM_BIT) #define ETH_MCR_OM_INTERNAL (0x1 << ETH_MCR_OM_BIT) #define ETH_MCR_OM_EXTERNAL (0x2 << ETH_MCR_OM_BIT)#define ETH_MCR_F (1 << 20)#define ETH_MCR_PM (1 << 19)#define ETH_MCR_PR (1 << 18)#define ETH_MCR_IF (1 << 17)#define ETH_MCR_PB (1 << 16)#define ETH_MCR_HO (1 << 15)#define ETH_MCR_HP (1 << 13)#define ETH_MCR_LCC (1 << 12)#define ETH_MCR_DBF (1 << 11)#define ETH_MCR_DTRY (1 << 10)#define ETH_MCR_ASTP (1 << 8)#define ETH_MCR_BOLMT_BIT 6#define ETH_MCR_BOLMT_MASK (0x3 << ETH_MCR_BOLMT_BIT) #define ETH_MCR_BOLMT_10 (0 << ETH_MCR_BOLMT_BIT) #define ETH_MCR_BOLMT_8 (1 << ETH_MCR_BOLMT_BIT) #define ETH_MCR_BOLMT_4 (2 << ETH_MCR_BOLMT_BIT) #define ETH_MCR_BOLMT_1 (3 << ETH_MCR_BOLMT_BIT)#define ETH_MCR_DC (1 << 5)#define ETH_MCR_TE (1 << 3)#define ETH_MCR_RE (1 << 2)/* MII Address Register (ETH_MIAR) */#define ETH_MIAR_PHY_ADDR_BIT 11#define ETH_MIAR_PHY_ADDR_MASK (0x1f << ETH_MIAR_PHY_ADDR_BIT)#define ETH_MIAR_MII_REG_BIT 6#define ETH_MIAR_MII_REG_MASK (0x1f << ETH_MIAR_MII_REG_BIT)#define ETH_MIAR_MII_WRITE (1 << 1)#define ETH_MIAR_MII_BUSY (1 << 0)/* Flow Control Register (ETH_FCR) */#define ETH_FCR_PAUSE_TIME_BIT 16#define ETH_FCR_PAUSE_TIME_MASK (0xffff << ETH_FCR_PAUSE_TIME_BIT)#define ETH_FCR_PCF (1 << 2)#define ETH_FCR_FCE (1 << 1)#define ETH_FCR_BUSY (1 << 0)/* PMT Control and Status Register (ETH_PMTR) */#define ETH_PMTR_GU (1 << 9)#define ETH_PMTR_RF (1 << 6)#define ETH_PMTR_MF (1 << 5)#define ETH_PMTR_RWK (1 << 2)#define ETH_PMTR_MPK (1 << 1)/* Receive Descriptor 0 (ETH_RD0) Bits */#define ETH_RD0_OWN (1 << 31)#define ETH_RD0_FF (1 << 30)#define ETH_RD0_FL_BIT 16#define ETH_RD0_FL_MASK (0x3fff << ETH_RD0_FL_BIT)#define ETH_RD0_ES (1 << 15)#define ETH_RD0_DE (1 << 14)#define ETH_RD0_LE (1 << 12)#define ETH_RD0_RF (1 << 11)#define ETH_RD0_MF (1 << 10)#define ETH_RD0_FD (1 << 9)#define ETH_RD0_LD (1 << 8)#define ETH_RD0_TL (1 << 7)#define ETH_RD0_CS (1 << 6)#define ETH_RD0_FT (1 << 5)#define ETH_RD0_WT (1 << 4)#define ETH_RD0_ME (1 << 3)#define ETH_RD0_DB (1 << 2)#define ETH_RD0_CE (1 << 1)/* Receive Descriptor 1 (ETH_RD1) Bits */#define ETH_RD1_RER (1 << 25)#define ETH_RD1_RCH (1 << 24)#define ETH_RD1_RBS2_BIT 11#define ETH_RD1_RBS2_MASK (0x7ff << ETH_RD1_RBS2_BIT)#define ETH_RD1_RBS1_BIT 0#define ETH_RD1_RBS1_MASK (0x7ff << ETH_RD1_RBS1_BIT)/* Transmit Descriptor 0 (ETH_TD0) Bits */#define ETH_TD0_OWN (1 << 31)#define ETH_TD0_FA (1 << 15)#define ETH_TD0_LOC (1 << 11)#define ETH_TD0_NC (1 << 10)#define ETH_TD0_LC (1 << 9)#define ETH_TD0_EC (1 << 8)#define ETH_TD0_HBF (1 << 7)#define ETH_TD0_CC_BIT 3#define ETH_TD0_CC_MASK (0xf << ETH_TD0_CC_BIT)#define ETH_TD0_ED (1 << 2)#define ETH_TD0_UF (1 << 1)#define ETH_TD0_DF (1 << 0)/* Transmit Descriptor 1 (ETH_TD1) Bits */#define ETH_TD1_IC (1 << 31)#define ETH_TD1_LS (1 << 30)#define ETH_TD1_FS (1 << 29)#define ETH_TD1_AC (1 << 26)#define ETH_TD1_TER (1 << 25)#define ETH_TD1_TCH (1 << 24)#define ETH_TD1_DPD (1 << 23)#define ETH_TD1_TBS2_BIT 11#define ETH_TD1_TBS2_MASK (0x7ff << ETH_TD1_TBS2_BIT)#define ETH_TD1_TBS1_BIT 0#define ETH_TD1_TBS1_MASK (0x7ff << ETH_TD1_TBS1_BIT)/************************************************************************* * WDT *************************************************************************/#define WDT_WTCSR (WDT_BASE + 0x00)#define WDT_WTCNT (WDT_BASE + 0x04)#define REG_WDT_WTCSR REG8(WDT_WTCSR)#define REG_WDT_WTCNT REG32(WDT_WTCNT)#define WDT_WTCSR_START (1 << 4)/************************************************************************* * OST *************************************************************************/#define OST_TER (OST_BASE + 0x00)#define OST_TRDR(n) (OST_BASE + 0x10 + ((n) * 0x20))#define OST_TCNT(n) (OST_BASE + 0x14 + ((n) * 0x20))#define OST_TCSR(n) (OST_BASE + 0x18 + ((n) * 0x20))#define OST_TCRB(n) (OST_BASE + 0x1c + ((n) * 0x20))#define REG_OST_TER REG8(OST_TER)#define REG_OST_TRDR(n) REG32(OST_TRDR((n)))#define REG_OST_TCNT(n) REG32(OST_TCNT((n)))#define REG_OST_TCSR(n) REG16(OST_TCSR((n)))#define REG_OST_TCRB(n) REG32(OST_TCRB((n)))#define OST_TCSR_BUSY (1 << 7)#define OST_TCSR_UF (1 << 6)#define OST_TCSR_UIE (1 << 5)#define OST_TCSR_CKS_BIT 0#define OST_TCSR_CKS_MASK (0x07 << OST_TCSR_CKS_BIT) #define OST_TCSR_CKS_PCLK_4 (0 << OST_TCSR_CKS_BIT) #define OST_TCSR_CKS_PCLK_16 (1 << OST_TCSR_CKS_BIT) #define OST_TCSR_CKS_PCLK_64 (2 << OST_TCSR_CKS_BIT) #define OST_TCSR_CKS_PCLK_256 (3 << OST_TCSR_CKS_BIT) #define OST_TCSR_CKS_RTCCLK (4 << OST_TCSR_CKS_BIT) #define OST_TCSR_CKS_EXTAL (5 << OST_TCSR_CKS_BIT)#define OST_TCSR0 OST_TCSR(0)#define OST_TCSR1 OST_TCSR(1)#define OST_TCSR2 OST_TCSR(2)#define OST_TRDR0 OST_TRDR(0)#define OST_TRDR1 OST_TRDR(1)#define OST_TRDR2 OST_TRDR(2)#define OST_TCNT0 OST_TCNT(0)#define OST_TCNT1 OST_TCNT(1)#define OST_TCNT2 OST_TCNT(2)#define OST_TCRB0 OST_TCRB(0)#define OST_TCRB1 OST_TCRB(1)#define OST_TCRB2 OST_TCRB(2)/************************************************************************* * UART *************************************************************************/#define IRDA_BASE UART0_BASE#define UART_BASE UART0_BASE#define UART_OFF 0x1000/* register offset */#define OFF_RDR (0x00) /* R 8b H'xx */#define OFF_TDR (0x00) /* W 8b H'xx */#define OFF_DLLR (0x00) /* RW 8b H'00 */#define OFF_DLHR (0x04) /* RW 8b H'00 */#define OFF_IER (0x04) /* RW 8b H'00 */⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -