tkdev_conf.h

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/*
 *----------------------------------------------------------------------
 *    T-Kernel
 *
 *    Copyright (C) 2004 by Ken Sakamura. All rights reserved.
 *    T-Kernel is distributed under the T-License.
 *----------------------------------------------------------------------
 *
 *    Version:   1.01.00
 *    Released by T-Engine Forum(http://www.t-engine.org) at 2004/6/28.
 *
 *----------------------------------------------------------------------
 */

/*
 *	tkdev_conf.h (MB87Q1100)
 *	Target System Configuration 
 */

#ifndef _TKDEV_CONF_
#define	_TKDEV_CONF_
/* Also included from assembler source */

/*
 * Timer
 *	register size W
 */
#define	TM_IRQ		14			/* Timer IRQ number */
#define	VECNO_TM	( EIT_IRQ(TM_IRQ) )	/* Timer vector */

#define	TMR(n)		( 0xfffe0000 + (n) )	/* Timer I/O address */

/* Register size W */
#define	TMRLD		TMR(0x00)	/* RW: Counter initial value */
#define	TMRVAL		TMR(0x04)	/* R-: Counter current value */
#define	TMRCTL		TMR(0x08)	/* RW: Control */
#define	TMRIC		TMR(0x0c)	/* -W: Clear interrupt */
#define	TMRRIS		TMR(0x10)	/* R-: Int. status (before mask) */
#define	TMRMIS		TMR(0x14)	/* R-: Int. status (after mask) */
#define	TMRBGL		TMR(0x18)	/* RW: Back ground load value */

/* TMRCTL */
#define	TC_OSC		0x0001		/* One shot */
#define	TC_TSIZE_32	0x0002		/* Counter 32 bit width */
#define	TC_PSCL_256	0x0008		/* Input clock 1/256 */
#define	TC_PSCL_16	0x0004		/*             1/16 */
#define	TC_PSCL_1	0x0000		/*             1/1 */
#define	TC_INTEN	0x0020		/* Enable interrupt */
#define	TC_PERIODIC	0x0040		/* Period */
#define	TC_FREERUN	0x0000		/* Free Running */
#define	TC_TEN		0x0080		/* Enable */

#define	TC_MODE		(TC_PERIODIC|TC_PSCL_1|TC_TSIZE_32)

/*
 * Timer interrupt level
 */
#define	TIMER_INTLEVEL		8

#endif /* _TKDEV_CONF_ */