main.c

DESCRIPTION =========== This example project shows how to use the IAR Embedded Workbench for ARM

//*----------------------------------------------------------------------------
//*         ATMEL Microcontroller Software Support  -  ROUSSET  -
//*----------------------------------------------------------------------------
//* The software is delivered "AS IS" without warranty or condition of any
//* kind, either express, implied or statutory. This includes without
//* limitation any warranty or condition with respect to merchantability or
//* fitness for any particular purpose, or against the infringements of
//* intellectual property rights of others.
//*----------------------------------------------------------------------------
//* File Name           : main.c
//* Object              : main application written in C
//* Creation            : ODi   06/26/2002
//*
//* Terminal settings:
//* SERIAL DEBUG PORT
//* ------------------
//* Communication speed: 115200 bps
//* Number of data bits:    8
//* Number of stop bits:    1
//* Parity:              none
//*
//* Jumplers:
//*  Set     J12   (VDDCORE)
//*  Set     J8    (VDDOSC VDDPLL)
//*  Set     J13   (FORCE POWER ON)
//*  Remove  J4    (BOOT MODE SELECT)
//*  Set     J21 on 1-2 position
//*
//*----------------------------------------------------------------------------

#include <stdio.h>
#include "AT91SAM9261_init.h"
#include "mmu.h"

#pragma data_alignment=16384
__no_init unsigned int TranslationTable [10000];

extern void AT91F_DBGU_Printk(char *);
extern void testloop(int);

//*----------------------------------------------------------------------------
//* \fn    AT91F_Dhrystone
//* \brief Count how many dhrystone have been executed in 1 sec
//*----------------------------------------------------------------------------
void AT91F_Dhrystone()
{
	unsigned int startTime, cnt, i;
	char msg[100];
	// Synchronize
	AT91C_BASE_RTTC->RTTC_RTMR = 0x8000;
	startTime = AT91C_BASE_RTTC->RTTC_RTVR;
	while (startTime == AT91C_BASE_RTTC->RTTC_RTVR);

	for (i = 0; i < 4; ++i) {
		// Synchronize
		//startTime = AT91F_RTTReadValue(AT91C_BASE_RTTC);
		startTime = AT91C_BASE_RTTC->RTTC_RTVR;
		cnt = 0;
		while (AT91C_BASE_RTTC->RTTC_RTVR == startTime) {
			testloop(1);
			++cnt;
		}
		sprintf(msg, "-I- %d Dhrystone per second\n\r", cnt);
		AT91F_DBGU_Printk(msg);
	}
}

//*----------------------------------------------------------------------------
//* \fn    AT91F_InitMMU
//* \brief Initialize MMU
//*----------------------------------------------------------------------------
void AT91F_InitMMU(unsigned int *pTranslationTable)
{
	int i;
	// Program the TTB
	AT91F_ARM_WriteTTB((unsigned int) pTranslationTable);
	// Program the domain access register
	AT91F_ARM_WriteDomain(0xC0000000); // domain 15: access are not checked

	// Reset table entries
	for (i = 0; i < 4096; ++i)
		pTranslationTable[i] = 0;
	// Program level 1 page table entry
	pTranslationTable[0x0] =
		(0x000 << 20) |     // Physical Address
		(1 << 10)     |     // Access in supervisor mode
		(15 << 5)     |     // Domain
		(1 << 4)      |
		(1 << 3)      |     // Cachable
		0x2;                // Set as 1 Mbyte section
	pTranslationTable[0x100] =
		(0x000 << 20) |     // Physical Address
		(1 << 10)     |     // Access in supervisor mode
		(15 << 5)     |     // Domain
		(1 << 4)      |
		(1 << 3)      |     // Cachable
		0x2;                // Set as 1 Mbyte section
	pTranslationTable[0x200] =
		(0x200 << 20) |     // Physical Address
		(1 << 10)     |     // Access in supervisor mode
		(15 << 5)     |     // Domain
		(1 << 4)      |
		(1 << 3)      |     // Cachable
		0x2;                // Set as 1 Mbyte section
	pTranslationTable[0xFFF] =
		(0xFFF << 20) |     // Physical Address
		(1 << 10)     |     // Access in supervisor mode
		(15 << 5)     |     // Domain
		(1 << 4)      |
		0x2;                // Set as 1 Mbyte section

	// Enable the MMU
	AT91F_EnableMMU();
}


int main()
{
  void (*pDhrystone)(void) = (void (*)()) ((unsigned int) AT91F_Dhrystone + 0x10000000);
	// Open PIO for DBGU
	AT91F_DBGU_CfgPIO();

	// Configure DBGU
	AT91F_US_Configure (
		(AT91PS_USART) AT91C_BASE_DBGU,          // DBGU base address
		Fmclk,
		AT91C_US_ASYNC_MODE,  // mode Register to be programmed
		115200 ,              // baudrate to be programmed
		0);                   // timeguard to be programmed

	// Enable Transmitter
	AT91F_US_EnableTx((AT91PS_USART) AT91C_BASE_DBGU);

  AT91F_DBGU_Printk("-I- Enter in main() section\n\r");

	AT91F_DBGU_Printk("-I- WO MMU & I+D Caches Disabled\n\r");
	AT91F_DisableICache();
	AT91F_DisableDCache();
	AT91F_Dhrystone();

	AT91F_DBGU_Printk("\n\r-I- WO MMU & I Cache Enabled\n\r");
	AT91F_EnableICache();
	AT91F_Dhrystone();

	AT91F_InitMMU(TranslationTable);

	AT91F_DBGU_Printk("\n\r-I- MMU & I Cache Enabled\n\r");
	AT91F_EnableICache();
	pDhrystone();

	AT91F_DBGU_Printk("\n\r-I- MMU & I+D Cache Enabled\n\r");
	AT91F_EnableDCache();
	pDhrystone();

  AT91F_DBGU_Printk("\n\r-I- End\n\r");

	while (1);
}