📄 iolpc2458.h
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__REG32 ALI :1;
__REG32 BEI :1;
__REG32 IDI :1;
__REG32 TI2 :1;
__REG32 TI3 :1;
__REG32 :5;
__REG32 ERRBIT :5;
__REG32 ERRDIR :1;
__REG32 ERRC :2;
__REG32 ALCBIT :8;
} __canicr_bits;
/* CAN interrupt enable register */
typedef struct {
__REG32 RIE :1;
__REG32 TIE1 :1;
__REG32 EIE :1;
__REG32 DOIE :1;
__REG32 WUIE :1;
__REG32 EPIE :1;
__REG32 ALIE :1;
__REG32 BEIE :1;
__REG32 IDIE :1;
__REG32 TIE2 :1;
__REG32 TIE3 :1;
__REG32 :21;
} __canier_bits;
/* CAN bus timing register */
typedef struct {
__REG32 BRP :10;
__REG32 :4;
__REG32 SJW :2;
__REG32 TSEG1 :4;
__REG32 TSEG2 :3;
__REG32 SAM :1;
__REG32 :8;
} __canbtr_bits;
/* CAN error warning limit register */
typedef struct {
__REG32 EWL :8;
__REG32 :24;
} __canewl_bits;
/* CAN status register */
typedef struct {
__REG32 RBS :1;
__REG32 DOS :1;
__REG32 TBS1 :1;
__REG32 TCS1 :1;
__REG32 RS :1;
__REG32 TS1 :1;
__REG32 ES :1;
__REG32 BS :1;
__REG32 /*RBS*/ :1;
__REG32 /*DOS*/ :1;
__REG32 TBS2 :1;
__REG32 TCS2 :1;
__REG32 /*RS*/ :1;
__REG32 TS2 :1;
__REG32 /*ES*/ :1;
__REG32 /*BS*/ :1;
__REG32 /*RBS*/ :1;
__REG32 /*DOS*/ :1;
__REG32 TBS3 :1;
__REG32 TCS3 :1;
__REG32 /*RS*/ :1;
__REG32 TS3 :1;
__REG32 /*ES*/ :1;
__REG32 /*BS*/ :1;
__REG32 :8;
} __cansr_bits;
/* CAN rx frame status register */
typedef struct {
__REG32 IDINDEX :10;
__REG32 BP :1;
__REG32 :5;
__REG32 DLC :4;
__REG32 :10;
__REG32 RTR :1;
__REG32 FF :1;
} __canrfs_bits;
/* CAN rx identifier register */
typedef union {
//CANxRID
struct {
__REG32 ID10_0 :11;
__REG32 :21;
};
//CANxRID
struct {
__REG32 ID29_18 :11;
__REG32 :21;
};
//CANxRID
struct {
__REG32 ID29_0 :29;
__REG32 :3;
};
} __canrid_bits;
/* CAN rx data register A */
typedef struct {
__REG32 DATA1 :8;
__REG32 DATA2 :8;
__REG32 DATA3 :8;
__REG32 DATA4 :8;
} __canrda_bits;
/* CAN rx data register B */
typedef struct {
__REG32 DATA5 :8;
__REG32 DATA6 :8;
__REG32 DATA7 :8;
__REG32 DATA8 :8;
} __canrdb_bits;
/* CAN tx frame information register */
typedef struct {
__REG32 PRIO :8;
__REG32 :8;
__REG32 DLC :4;
__REG32 :10;
__REG32 RTR :1;
__REG32 FF :1;
} __cantfi_bits;
/* CAN tx identifier register */
typedef union {
//CANxTIDy
struct {
__REG32 ID10_0 :11;
__REG32 :21;
};
//CANxTIDy
struct {
__REG32 ID29_18 :11;
__REG32 :21;
};
//CANxTIDy
struct {
__REG32 ID29_0 :29;
__REG32 :3;
};
} __cantid_bits;
/* CAN tx data register A */
typedef struct {
__REG32 DATA1 :8;
__REG32 DATA2 :8;
__REG32 DATA3 :8;
__REG32 DATA4 :8;
} __cantda_bits;
/* CAN tx data register B */
typedef struct {
__REG32 DATA5 :8;
__REG32 DATA6 :8;
__REG32 DATA7 :8;
__REG32 DATA8 :8;
} __cantdb_bits;
/* USB - Device Interrupt Status Register */
/* OTG_status and control Register */
typedef union {
// USBPORTSEL
struct {
__REG32 PORTSEL : 2;
__REG32 :30;
};
// OTGSTCTRL
struct {
__REG32 PORT_FUNC : 2;
__REG32 TMR_SCALE : 2;
__REG32 TMR_MODE : 1;
__REG32 TMR_EN : 1;
__REG32 TMR_RST : 1;
__REG32 : 1;
__REG32 B_HNP_TRACK : 1;
__REG32 A_HNP_TRACK : 1;
__REG32 PU_REMOVED : 1;
__REG32 : 5;
__REG32 TMR_CNT :16;
};
} __usbportsel_bits;
/* USB Clock Control register (USBClkCtrl - 0xFFE0 CFF4) */
/* OTG_clock Registers */
typedef union {
// USBCLKCTRL
struct{
__REG32 : 1;
__REG32 DEV_CLK_EN : 1;
__REG32 : 1;
__REG32 PORTSEL_CLK_EN : 1;
__REG32 AHB_CLK_EN : 1;
__REG32 :27;
};
// OTGCLKCTRL
struct{
__REG32 _HOST_CLK_EN : 1;
__REG32 _DEV_CLK_EN : 1;
__REG32 _I2C_CLK_EN : 1;
__REG32 _OTG_CLK_EN : 1;
__REG32 _AHB_CLK_EN : 1;
__REG32 :27;
};
} __usbclkctrl_bits;
/* USB Clock Status register (USBClkSt - 0xFFE0 CFF8) */
/* OTG_status Registers */
typedef union {
// USBCLKST
struct{
__REG32 : 1;
__REG32 DEV_CLK_ON : 1;
__REG32 : 1;
__REG32 PORTSEL_CLK_ON : 1;
__REG32 AHB_CLK_ON : 1;
__REG32 :27;
};
// OTGCLKST
struct{
__REG32 _HOST_CLK_ON : 1;
__REG32 _DEV_CLK_ON : 1;
__REG32 _I2C_CLK_ON : 1;
__REG32 _OTG_CLK_ON : 1;
__REG32 _AHB_CLK_ON : 1;
__REG32 :27;
};
} __usbclkst_bits;
/* USB - Device Interrupt Status Register */
typedef struct {
__REG32 USB_INT_REQ_LP : 1;
__REG32 USB_INT_REQ_HP : 1;
__REG32 USB_INT_REQ_DMA : 1;
__REG32 USB_HOST_INT : 1;
__REG32 USB_ATX_INT : 1;
__REG32 USB_OTG_INT : 1;
__REG32 USB_I2C_INT : 1;
__REG32 : 1;
__REG32 USB_NEED_CLOCK : 1;
__REG32 :22;
__REG32 EN_USB_INTS : 1;
} __usbints_bits;
/* USB - Device Interrupt Status Register */
/* USB - Device Interrupt Enable Register */
/* USB - Device Interrupt Clear Register */
/* USB - Device Interrupt Set Register */
typedef struct {
__REG32 FRAME : 1;
__REG32 EP_FAST : 1;
__REG32 EP_SLOW : 1;
__REG32 DEV_STAT : 1;
__REG32 CCEMTY : 1;
__REG32 CDFULL : 1;
__REG32 RXENDPKT : 1;
__REG32 TXENDPKT : 1;
__REG32 EP_RLZED : 1;
__REG32 ERR_INT : 1;
__REG32 :22;
} __usbdevintst_bits;
/* USB - Device Interrupt Priority Register */
typedef struct {
__REG8 FRAME : 1;
__REG8 EP_FAST : 1;
__REG8 : 6;
} __usbdevintpri_bits;
/* USB - Endpoint Interrupt Status Register */
/* USB - Endpoint Interrupt Enable Register */
/* USB - Endpoint Interrupt Clear Register */
/* USB - Endpoint Interrupt Set Register */
/* USB - Endpoint Interrupt Priority Register */
typedef struct {
__REG32 EP_0RX : 1;
__REG32 EP_0TX : 1;
__REG32 EP_1RX : 1;
__REG32 EP_1TX : 1;
__REG32 EP_2RX : 1;
__REG32 EP_2TX : 1;
__REG32 EP_3RX : 1;
__REG32 EP_3TX : 1;
__REG32 EP_4RX : 1;
__REG32 EP_4TX : 1;
__REG32 EP_5RX : 1;
__REG32 EP_5TX : 1;
__REG32 EP_6RX : 1;
__REG32 EP_6TX : 1;
__REG32 EP_7RX : 1;
__REG32 EP_7TX : 1;
__REG32 EP_8RX : 1;
__REG32 EP_8TX : 1;
__REG32 EP_9RX : 1;
__REG32 EP_9TX : 1;
__REG32 EP_10RX : 1;
__REG32 EP_10TX : 1;
__REG32 EP_11RX : 1;
__REG32 EP_11TX : 1;
__REG32 EP_12RX : 1;
__REG32 EP_12TX : 1;
__REG32 EP_13RX : 1;
__REG32 EP_13TX : 1;
__REG32 EP_14RX : 1;
__REG32 EP_14TX : 1;
__REG32 EP_15RX : 1;
__REG32 EP_15TX : 1;
} __usbepintst_bits;
/* USB - Realize Enpoint Register */
/* USB - DMA Request Status Register */
/* USB - DMA Request Clear Register */
/* USB - DMA Request Set Regiser */
/* USB - EP DMA Status Register */
/* USB - EP DMA Enable Register */
/* USB - EP DMA Disable Register */
/* USB - New DD Request Interrupt Status Register */
/* USB - New DD Request Interrupt Clear Register */
/* USB - New DD Request Interrupt Set Register */
/* USB - End Of Transfer Interrupt Status Register */
/* USB - End Of Transfer Interrupt Clear Register */
/* USB - End Of Transfer Interrupt Set Register */
/* USB - System Error Interrupt Status Register */
/* USB - System Error Interrupt Clear Register */
/* USB - System Error Interrupt Set Register */
typedef struct {
__REG32 EP0 : 1;
__REG32 EP1 : 1;
__REG32 EP2 : 1;
__REG32 EP3 : 1;
__REG32 EP4 : 1;
__REG32 EP5 : 1;
__REG32 EP6 : 1;
__REG32 EP7 : 1;
__REG32 EP8 : 1;
__REG32 EP9 : 1;
__REG32 EP10 : 1;
__REG32 EP11 : 1;
__REG32 EP12 : 1;
__REG32 EP13 : 1;
__REG32 EP14 : 1;
__REG32 EP15 : 1;
__REG32 EP16 : 1;
__REG32 EP17 : 1;
__REG32 EP18 : 1;
__REG32 EP19 : 1;
__REG32 EP20 : 1;
__REG32 EP21 : 1;
__REG32 EP22 : 1;
__REG32 EP23 : 1;
__REG32 EP24 : 1;
__REG32 EP25 : 1;
__REG32 EP26 : 1;
__REG32 EP27 : 1;
__REG32 EP28 : 1;
__REG32 EP29 : 1;
__REG32 EP30 : 1;
__REG32 EP31 : 1;
} __usbreep_bits;
/* USB - Endpoint Index Register */
typedef struct {
__REG32 PHY_ENDP : 5;
__REG32 :27;
} __usbepin_bits;
/* USB - MaxPacketSize Register */
typedef struct {
__REG32 MPS :10;
__REG32 :22;
} __usbmaxpsize_bits;
/* USB - Receive Packet Length Register */
typedef struct {
__REG32 PKT_LNGTH :10;
__REG32 DV : 1;
__REG32 PKT_RDY : 1;
__REG32 :20;
} __usbrxplen_bits;
/* USB - Transmit Packet Length Register */
typedef struct {
__REG32 PKT_LNGHT :10;
__REG32 :22;
} __usbtxplen_bits;
/* USB - Control Register */
typedef struct {
__REG32 RD_EN : 1;
__REG32 WR_EN : 1;
__REG32 LOG_ENDPOINT : 4;
__REG32 :26;
} __usbctrl_bits;
/* USB - Command Code Register */
typedef struct {
__REG32 : 8;
__REG32 CMD_PHASE : 8;
__REG32 CMD_CODE : 8;
__REG32 : 8;
} __usbcmdcode_bits;
/* USB - Command Data Register */
typedef struct {
__REG32 CMD_DATA : 8;
__REG32 :24;
} __usbcmddata_bits;
/* USB - DMA Interrupt Status Register */
/* USB - DMA Interrupt Enable Register */
typedef struct {
__REG32 EOT : 1;
__REG32 NDDR : 1;
__REG32 ERR : 1;
__REG32 :29;
} __usbdmaintst_bits;
/* HcRevision Register */
typedef struct {
__REG32 REV : 8;
__REG32 :24;
} __hcrevision_bits;
/* HcControl Register */
typedef struct {
__REG32 CBSR : 2;
__REG32 PLE : 1;
__REG32 IE : 1;
__REG32 CLE : 1;
__REG32 BLE : 1;
__REG32 HCFS : 2;
__REG32 IR : 1;
__REG32 RWC : 1;
__REG32 RWE : 1;
__REG32 :21;
} __hccontrol_bits;
/* HcCommandStatus Register */
typedef struct {
__REG32 HCR : 1;
__REG32 CLF : 1;
__REG32 BLF : 1;
__REG32 OCR : 1;
__REG32 :12;
__REG32 SOC : 2;
__REG32 :14;
} __hccommandstatus_bits;
/* HcInterruptStatus Register */
typedef struct {
__REG32 SO : 1;
__REG32 WDH : 1;
__REG32 SF : 1;
__REG32 RD : 1;
__REG32 UE : 1;
__REG32 FNO : 1;
__REG32 RHSC : 1;
__REG32 :23;
__REG32 OC : 1;
__REG32 : 1;
} __hcinterruptstatus_bits;
/* HcInterruptEnable Register
HcInterruptDisable Register */
typedef struct {
__REG32 SO : 1;
__REG32 WDH : 1;
__REG32 SF : 1;
__REG32 RD : 1;
__REG32 UE : 1;
__REG32 FNO : 1;
__REG32 RHSC : 1;
__REG32 :23;
__REG32 OC : 1;
__REG32 MIE : 1;
} __hcinterruptenable_bits;
/* HcHCCA Register */
typedef struct {
__REG32 : 8;
__REG32 HCCA :24;
} __hchcca_bits;
/* HcPeriodCurrentED Register */
typedef struct {
__REG32 : 4;
__REG32 PCED :28;
} __hcperiodcurrented_bits;
/* HcControlHeadED Registerr */
typedef struct {
__REG32 : 4;
__REG32 CHED :28;
} __hccontrolheaded_bits;
/* HcControlCurrentED Register */
typedef struct {
__REG32 : 4;
__REG32 CCED :28;
} __hccontrolcurrented_bits;
/* HcBulkHeadED Register */
typedef struct {
__REG32 : 4;
__REG32 BHED :28;
} __hcbulkheaded_bits;
/* HcBulkCurrentED Register */
typedef struct {
__REG32 : 4;
__REG32 BCED :28;
} __hcbulkcurrented_bits;
/* HcDoneHead Register */
typedef struct {
__REG32 : 4;
__REG32 DH :28;
} __hcdonehead_bits;
/* HcFmInterval Register */
typedef struct {
__REG32 FI :14;
__REG32 : 2;
__REG32 FSMPS :15;
__REG32 FIT : 1;
} __hcfminterval_bits;
/* HcFmRemaining Register */
typedef struct {
__REG32 FR :1⌨️ 快捷键说明
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