📄 iolpc2458.h
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typedef struct{
__REG32 FD : 1;
__REG32 FLC : 1;
__REG32 HFE : 1;
__REG32 DLYCRC : 1;
__REG32 CRCEN : 1;
__REG32 PADCRCEN : 1;
__REG32 VLANCRCEN : 1;
__REG32 ADPE : 1;
__REG32 PPE : 1;
__REG32 LPE : 1;
__REG32 : 2;
__REG32 NB : 1;
__REG32 BP : 1;
__REG32 ED : 1;
__REG32 :17;
}__mac2_bits;
/* Back-to-Back Inter-Packet-Gap Register */
typedef struct{
__REG32 IPG : 7;
__REG32 :25;
}__ipgt_bits;
/* Non Back-to-Back Inter-Packet-Gap Register */
typedef struct{
__REG32 IPGR2 : 7;
__REG32 : 1;
__REG32 IPGR1 : 7;
__REG32 :17;
}__ipgr_bits;
/*Collision Window / Retry Register */
typedef struct{
__REG32 RM : 4;
__REG32 : 4;
__REG32 CW : 6;
__REG32 :18;
}__clrt_bits;
/* Maximum Frame Register */
typedef struct{
__REG32 MAXF :16;
__REG32 :16;
}__maxf_bits;
/* PHY Support Register */
typedef struct{
__REG32 : 8;
__REG32 SPEED : 1;
__REG32 :23;
}__supp_bits;
/* Test Register */
typedef struct{
__REG32 SPQ : 1;
__REG32 TP : 1;
__REG32 TB : 1;
__REG32 :29;
}__test_bits;
/* MII Mgmt Configuration Register */
typedef struct{
__REG32 SI : 1;
__REG32 SP : 1;
__REG32 CS : 3;
__REG32 :10;
__REG32 RSTMIIMGMT : 1;
__REG32 :16;
}__mcfg_bits;
/* MII Mgmt Command Register */
typedef struct{
__REG32 READ : 1;
__REG32 SCAN : 1;
__REG32 :30;
}__mcmd_bits;
/* MII Mgmt Address Register */
typedef struct{
__REG32 REGADDR : 5;
__REG32 : 3;
__REG32 PHY_ADDR : 5;
__REG32 :19;
}__madr_bits;
/* MII Mgmt Write Data Register */
typedef struct{
__REG32 WRITEDATA :16;
__REG32 :16;
}__mwtd_bits;
/* MII Mgmt Read Data Register */
typedef struct{
__REG32 READDATA :16;
__REG32 :16;
}__mrdd_bits;
/* MII Mgmt Indicators Register */
typedef struct{
__REG32 BUSY : 1;
__REG32 SCANNING : 1;
__REG32 NOT_VALID : 1;
__REG32 MII_LINK_FAIL : 1;
__REG32 :28;
}__mind_bits;
/* Station Address 0 Register */
typedef struct{
__REG32 STATION_ADDR_2 : 8;
__REG32 STATION_ADDR_1 : 8;
__REG32 :16;
}__sa0_bits;
/* Station Address 1 Register */
typedef struct{
__REG32 STATION_ADDR_4 : 8;
__REG32 STATION_ADDR_3 : 8;
__REG32 :16;
}__sa1_bits;
/* Station Address 2 Register */
typedef struct{
__REG32 STATION_ADDR_6 : 8;
__REG32 STATION_ADDR_5 : 8;
__REG32 :16;
}__sa2_bits;
/* Command Register */
typedef struct{
__REG32 RXENABLE : 1;
__REG32 TXENABLE : 1;
__REG32 : 1;
__REG32 REGRESET : 1;
__REG32 TXRESET : 1;
__REG32 RXRESET : 1;
__REG32 PASSRUNTFRAME : 1;
__REG32 PASSRXFILTER : 1;
__REG32 TXFLOWCONTROL : 1;
__REG32 RMII : 1;
__REG32 FULLDUPLEX : 1;
__REG32 :21;
}__command_bits;
/* Status Register */
typedef struct{
__REG32 RXSTATUS : 1;
__REG32 TXSTATUS : 1;
__REG32 :30;
}__status_bits;
/* Receive Number of Descriptors Register */
typedef struct{
__REG32 RXDESCRIPTORNUMBER :16;
__REG32 :16;
}__rxdescrn_bits;
/* Receive Produce Index Register */
typedef struct{
__REG32 RXPRODUCDINDEX :16;
__REG32 :16;
}__rxprodind_bits;
/* Receive Consume Index Register */
typedef struct{
__REG32 RXCONSUMEINDEX :16;
__REG32 :16;
}__rxcomind_bits;
/* Transmit Number of Descriptors Register */
typedef struct{
__REG32 TXDESCRIPTORNUMBER :16;
__REG32 :16;
}__txdescrn_bits;
/* Transmit Produce Index Register */
typedef struct{
__REG32 TXPRODUCDINDEX :16;
__REG32 :16;
}__txprodind_bits;
/* Transmit Consume Index Register */
typedef struct{
__REG32 TXCONSUMEINDEX :16;
__REG32 :16;
}__txcomind_bits;
/* Transmit Status Vector 0 Register */
typedef struct{
__REG32 CCR_ERR : 1;
__REG32 LCERR : 1;
__REG32 LOOR : 1;
__REG32 DONE : 1;
__REG32 MULTICAST : 1;
__REG32 BROADCAST : 1;
__REG32 PD : 1;
__REG32 ED : 1;
__REG32 EC : 1;
__REG32 LC : 1;
__REG32 GIANT : 1;
__REG32 UNDERRUN : 1;
__REG32 TB :16;
__REG32 CF : 1;
__REG32 PAUSE : 1;
__REG32 BACKPRESSURE : 1;
__REG32 VLAN : 1;
}__tsv0_bits;
/* Transmit Status Vector 1 Register */
typedef struct{
__REG32 TBC :16;
__REG32 TCC : 4;
__REG32 :12;
}__tsv1_bits;
/* Receive Status Vector Register */
typedef struct{
__REG32 RBC :16;
__REG32 PPI : 1;
__REG32 RXDVEPS : 1;
__REG32 CEPS : 1;
__REG32 RCV : 1;
__REG32 CRC_ERR : 1;
__REG32 LCE : 1;
__REG32 LOOR : 1;
__REG32 R_OK : 1;
__REG32 MULTICAST : 1;
__REG32 BROADCAST : 1;
__REG32 DN : 1;
__REG32 CF : 1;
__REG32 PAUSE : 1;
__REG32 UO : 1;
__REG32 VLAN : 1;
__REG32 : 1;
}__rsv_bits;
/* Flow Control Counter Register */
typedef struct{
__REG32 MC :16;
__REG32 PT :16;
}__fwctrlcnt_bits;
/* Flow Control Status Register */
typedef struct{
__REG32 MCC :16;
__REG32 :16;
}__fwctrlstat_bits;
/* Receive Filter Control Register */
typedef struct{
__REG32 AUE : 1;
__REG32 ABE : 1;
__REG32 AME : 1;
__REG32 AUHE : 1;
__REG32 AMHE : 1;
__REG32 APE : 1;
__REG32 : 6;
__REG32 MPEWOL : 1;
__REG32 RXFEWOL : 1;
__REG32 :18;
}__rxflctrl_bits;
/* Receive Filter WoL Status Register */
typedef struct{
__REG32 AUWOL : 1;
__REG32 ABWOL : 1;
__REG32 AMWOL : 1;
__REG32 AUHWOL : 1;
__REG32 AMHWOL : 1;
__REG32 APWOL : 1;
__REG32 : 1;
__REG32 RXFWOL : 1;
__REG32 MPWOL : 1;
__REG32 :23;
}__rxflwolstat_bits;
/* Receive Filter WoL Clear Register */
typedef struct{
__REG32 AUWOLC : 1;
__REG32 ABWOLC : 1;
__REG32 AMWOLC : 1;
__REG32 AUHWOLC : 1;
__REG32 AMHWOLC : 1;
__REG32 APWOLC : 1;
__REG32 : 1;
__REG32 RXFWOLC : 1;
__REG32 MPWOLC : 1;
__REG32 :23;
}__rxflwolclr_bits;
/* Interrupt Status Register */
typedef struct{
__REG32 RXOVERRUNINT : 1;
__REG32 RXERRORINT : 1;
__REG32 RXFINISHEDINT : 1;
__REG32 RXDONEINT : 1;
__REG32 TXUNDERRUNINT : 1;
__REG32 TXERRORINT : 1;
__REG32 TXFINISHEDINT : 1;
__REG32 TXDONEINT : 1;
__REG32 : 4;
__REG32 SOFTINT : 1;
__REG32 WAKEUPINT : 1;
__REG32 :18;
}__intstat_bits;
/* Interrupt Enable Register */
typedef struct{
__REG32 RXOVERRUNINTEN : 1;
__REG32 RXERRORINTEN : 1;
__REG32 RXFINISHEDINTEN : 1;
__REG32 RXDONEINTEN : 1;
__REG32 TXUNDERRUNINTEN : 1;
__REG32 TXERRORINTEN : 1;
__REG32 TXFINISHEDINTEN : 1;
__REG32 TXDONEINTEN : 1;
__REG32 : 4;
__REG32 SOFTINTEN : 1;
__REG32 WAKEUPINTEN : 1;
__REG32 :18;
}__intena_bits;
/* Interrupt Clear Register */
typedef struct{
__REG32 RXOVERRUNINTCLR : 1;
__REG32 RXERRORINTCLR : 1;
__REG32 RXFINISHEDINTCLR: 1;
__REG32 RXDONEINTCLR : 1;
__REG32 TXUNDERRUNINTCLR: 1;
__REG32 TXERRORINTCLR : 1;
__REG32 TXFINISHEDINTCLR: 1;
__REG32 TXDONEINTCLR : 1;
__REG32 : 4;
__REG32 SOFTINTCLR : 1;
__REG32 WAKEUPINTCLR : 1;
__REG32 :18;
}__intclr_bits;
/* Interrupt Set Register */
typedef struct{
__REG32 RXOVERRUNINTSET : 1;
__REG32 RXERRORINTSET : 1;
__REG32 RXFINISHEDINTSET: 1;
__REG32 RXDONEINTSET : 1;
__REG32 TXUNDERRUNINTSET: 1;
__REG32 TXERRORINTSET : 1;
__REG32 TXFINISHEDINTSET: 1;
__REG32 TXDONEINTSET : 1;
__REG32 : 4;
__REG32 SOFTINTSET : 1;
__REG32 WAKEUPINTSET : 1;
__REG32 :18;
}__intset_bits;
/* Power Down Register */
typedef struct{
__REG32 :31;
__REG32 POWERDOWN : 1;
}__pwrdn_bits;
/* CAN acceptance filter mode register */
typedef struct {
__REG32 ACCOFF :1;
__REG32 ACCBP :1;
__REG32 EFCAN :1;
__REG32 :29;
} __afmr_bits;
/* CAN LUT Error Register */
typedef struct {
__REG32 LUTERR :1;
__REG32 :31;
} __luterr_bits;
/* Global FullCANInterrupt Enable register */
typedef struct {
__REG32 FCANIE :1;
__REG32 :31;
} __fcanie_bits;
/* FullCAN Interrupt and Capture registers 0 */
typedef struct {
__REG32 INTPND0 :1;
__REG32 INTPND1 :1;
__REG32 INTPND2 :1;
__REG32 INTPND3 :1;
__REG32 INTPND4 :1;
__REG32 INTPND5 :1;
__REG32 INTPND6 :1;
__REG32 INTPND7 :1;
__REG32 INTPND8 :1;
__REG32 INTPND9 :1;
__REG32 INTPND10 :1;
__REG32 INTPND11 :1;
__REG32 INTPND12 :1;
__REG32 INTPND13 :1;
__REG32 INTPND14 :1;
__REG32 INTPND15 :1;
__REG32 INTPND16 :1;
__REG32 INTPND17 :1;
__REG32 INTPND18 :1;
__REG32 INTPND19 :1;
__REG32 INTPND20 :1;
__REG32 INTPND21 :1;
__REG32 INTPND22 :1;
__REG32 INTPND23 :1;
__REG32 INTPND24 :1;
__REG32 INTPND25 :1;
__REG32 INTPND26 :1;
__REG32 INTPND27 :1;
__REG32 INTPND28 :1;
__REG32 INTPND29 :1;
__REG32 INTPND30 :1;
__REG32 INTPND31 :1;
} __fcanic0_bits;
/* FullCAN Interrupt and Capture registers 1 */
typedef struct {
__REG32 INTPND32 :1;
__REG32 INTPND33 :1;
__REG32 INTPND34 :1;
__REG32 INTPND35 :1;
__REG32 INTPND36 :1;
__REG32 INTPND37 :1;
__REG32 INTPND38 :1;
__REG32 INTPND39 :1;
__REG32 INTPND40 :1;
__REG32 INTPND41 :1;
__REG32 INTPND42 :1;
__REG32 INTPND43 :1;
__REG32 INTPND44 :1;
__REG32 INTPND45 :1;
__REG32 INTPND46 :1;
__REG32 INTPND47 :1;
__REG32 INTPND48 :1;
__REG32 INTPND49 :1;
__REG32 INTPND50 :1;
__REG32 INTPND51 :1;
__REG32 INTPND52 :1;
__REG32 INTPND53 :1;
__REG32 INTPND54 :1;
__REG32 INTPND55 :1;
__REG32 INTPND56 :1;
__REG32 INTPND57 :1;
__REG32 INTPND58 :1;
__REG32 INTPND59 :1;
__REG32 INTPND60 :1;
__REG32 INTPND61 :1;
__REG32 INTPND62 :1;
__REG32 INTPND63 :1;
} __fcanic1_bits;
/* CAN central transmit status register */
typedef struct {
__REG32 TS1 : 1;
__REG32 TS2 : 1;
__REG32 : 6;
__REG32 TBS1 : 1;
__REG32 TBS2 : 1;
__REG32 : 6;
__REG32 TCS1 : 1;
__REG32 TCS2 : 1;
__REG32 :14;
} __cantxsr_bits;
/* CAN central receive status register */
typedef struct {
__REG32 RS1 : 1;
__REG32 RS2 : 1;
__REG32 : 6;
__REG32 RBS1 : 1;
__REG32 RBS2 : 1;
__REG32 : 6;
__REG32 DOS1 : 1;
__REG32 DOS2 : 1;
__REG32 :14;
} __canrxsr_bits;
/* CAN miscellaneous status register */
typedef struct {
__REG32 E1 : 1;
__REG32 E2 : 1;
__REG32 : 6;
__REG32 BS1 : 1;
__REG32 BS2 : 1;
__REG32 :22;
} __canmsr_bits;
/* CAN mode register */
typedef struct {
__REG32 RM :1;
__REG32 LOM :1;
__REG32 STM :1;
__REG32 TPM :1;
__REG32 SM :1;
__REG32 RPM :1;
__REG32 :1;
__REG32 TM :1;
__REG32 :24;
} __canmod_bits;
/* CAN command register */
typedef struct {
__REG32 TR :1;
__REG32 AT :1;
__REG32 RRB :1;
__REG32 CDO :1;
__REG32 SRR :1;
__REG32 STB1 :1;
__REG32 STB2 :1;
__REG32 STB3 :1;
__REG32 :24;
} __cancmr_bits;
/* CAN global status register */
typedef struct {
__REG32 RBS :1;
__REG32 DOS :1;
__REG32 TBS :1;
__REG32 TCS :1;
__REG32 RS :1;
__REG32 TS :1;
__REG32 ES :1;
__REG32 BS :1;
__REG32 :8;
__REG32 RXERR :8;
__REG32 TXERR :8;
} __cangsr_bits;
/* CAN interrupt capture register */
typedef struct {
__REG32 RI :1;
__REG32 TI1 :1;
__REG32 EI :1;
__REG32 DOI :1;
__REG32 WUI :1;
__REG32 EPI :1;
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