📄 adjust.c
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CScalerSetBit(_FS_DELAY_FINE_TUNING_43, ~_BIT1, 0x00);
CScalerSetByte(_IVS2DVS_DELAY_LINES_40, pData[14]);
CScalerSetByte(_IV_DV_DELAY_CLK_ODD_41, pData[15]);
return pData[14];
}
#if(_SCALER_TYPE == _RTD2323) //Updated by Realtek at 20050617
//--------------------------------------------------
// Description : Set display clock (Dclk) frequency in kHz
// Input Value : ulFreq --> Target Dclk frequency
// Output Value : None
//--------------------------------------------------
void CAdjustDPLL(LWORD ulFreq)
{
WORD mcode;
BYTE div;
// We want to set DPLL offset to middle(2048), so the target DPLL M/N setting should be 16/15 of target frequency.
mcode = ulFreq * 8 * _DPLL_N_CODE * 16 / ((LWORD)_RTD_XTAL * 15);
if(mcode > 255)
{
div = 1; // Output DPLL for DCLK
mcode = (mcode + 2) >> 2; // Round to integer
}
else
{
div = 2; // Output DPLL/2 for DCLK
mcode = (mcode + 1) >> 1; // Round to integer
}
// Original Formula : M_Code/Ich = 17.6 must be constant
// Ich = M_Code * 10 / 176
// 2*Ich = M_Code * 20 / 176 , set D0[5] to 0, then I = 2 * Ich
// I = 2 * Ich = 2.5u + D0[0]*2.5u + D0[1]*5u + D0[2]*10u + D0[3]*20u + D0[4]*30u (A)
// 2*I = 4 * Ich = 5u + D0[0]*5u + D0[1]*10u + D0[2]*20u + D0[3]*40u + D0[4]*60u (A)
// Calculate the 4 * Ich,
pData[5] = ((WORD)mcode * 4 * 10 / 176) - 5;
pData[6] = 0x00;
if(pData[5] >= 60)
{
pData[5] -= 60;
pData[6] |= 0x10;
}
if(pData[5] >= 40)
{
pData[5] -= 40;
pData[6] |= 0x08;
}
if(pData[5] >= 20)
{
pData[5] -= 20;
pData[6] |= 0x04;
}
if(pData[5] >= 10)
{
pData[5] -= 10;
pData[6] |= 0x02;
}
if(pData[5] >= 5)
{
pData[5] -= 5;
pData[6] |= 0x01;
}
pData[0] = mcode - 2;
#if(_M2PLL_USE == _ON)
pData[1] = ((1 == div) ? 0x00 : 0x10) | ((_DPLL_N_CODE / _RTD_M2PLL_RATIO) - 2);
#else
pData[1] = ((1 == div) ? 0x00 : 0x10) | (_DPLL_N_CODE - 2);
#endif
pData[2] = 0x40 | pData[6];
pData[3] = 0x0f;
CScalerWrite(_DPLL_M_AE, 4, pData, _AUTOINC);
// Dclk frequency in Hz
((LWORD *)pData)[0] = (LWORD)_RTD_XTAL * 1000 / (div * 2) * mcode / _DPLL_N_CODE;
// Offset resolution (Dclk / 2^15) in Hz
((LWORD *)pData)[1] = ((LWORD *)pData)[0] >> 15;
// Target frequency of Dclk in Hz
mcode = (((LWORD *)pData)[0] - (ulFreq * 1000)) / ((LWORD *)pData)[1];
mcode = mcode & 0x0fff;
//Enable DDS spread spectrum output function
CScalerSetBit(_FIXED_LAST_LINE_CTRL_BB, ~_BIT0, _BIT0);
CAdjustDclkOffset(mcode);
}
//#elif((_SCALER_TYPE == _RTD2023L) || (_SCALER_TYPE == _RTD2023S))
//versoion 200D
#elif((_SCALER_TYPE == _RTD2023L) || (_SCALER_TYPE == _RTD2023S) || (_SCALER_TYPE == _RTD2023L_SHRINK))
//--------------------------------------------------
// Description : Set display clock (Dclk) frequency in kHz
// Input Value : ulFreq --> Target Dclk frequency
// Output Value : None
//--------------------------------------------------
void CAdjustDPLL(LWORD ulFreq)
{
WORD mcode;
BYTE div;
// We want to set DPLL offset to middle(2048), so the target DPLL M/N setting should be 16/15 of target frequency.
mcode = ulFreq * 8 * _DPLL_N_CODE * 16 / ((LWORD)_RTD_XTAL * 15);
if(mcode > 255)
{
div = 1; // Output DPLL for DCLK
mcode = (mcode + 2) >> 2; // Round to integer
}
else
{
div = 2; // Output DPLL/2 for DCLK
mcode = (mcode + 1) >> 1; // Round to integer
}
// Original Formula : M_Code/Ich = 17.6 must be constant
// Ich = M_Code * 10 / 176
// Ich = 1u + D0[0]*1u + D0[1]*2u + D0[2]*4u + D0[3]*8u (A)
// Calculate the 4 * Ich,
pData[5] = ((WORD)mcode * 10 / 176) - 1;
pData[6] = 0x00;
if(pData[5] >= 8)
{
pData[5] -= 8;
pData[6] |= 0x80;
}
if(pData[5] >= 4)
{
pData[5] -= 4;
pData[6] |= 0x04;
}
if(pData[5] >= 2)
{
pData[5] -= 2;
pData[6] |= 0x02;
}
if(pData[5] >= 1)
{
pData[5] -= 1;
pData[6] |= 0x01;
}
pData[0] = mcode - 2;
#if(_M2PLL_USE == _ON)
pData[1] = ((1 == div) ? 0x00 : 0x10) | ((_DPLL_N_CODE / _RTD_M2PLL_RATIO) - 2);
#else
pData[1] = ((1 == div) ? 0x00 : 0x10) | (_DPLL_N_CODE - 2);
#endif
pData[2] = 0x40 | pData[6];
pData[3] = 0x0f;
CScalerWrite(_DPLL_M_AE, 4, pData, _AUTOINC);
// Dclk frequency in Hz
((LWORD *)pData)[0] = (LWORD)_RTD_XTAL * 1000 / (div * 2) * mcode / _DPLL_N_CODE;
// Offset resolution (Dclk / 2^15) in Hz
((LWORD *)pData)[1] = ((LWORD *)pData)[0] >> 15;
// Target frequency of Dclk in Hz
mcode = (((LWORD *)pData)[0] - (ulFreq * 1000)) / ((LWORD *)pData)[1];
mcode = mcode & 0x0fff;
//Enable DDS spread spectrum output function
CScalerSetBit(_FIXED_LAST_LINE_CTRL_BB, ~_BIT0, _BIT0);
CAdjustDclkOffset(mcode);
}
#endif
//--------------------------------------------------
// Description : Check if the ADC clock (IHTotal) is out of range. Range = (BackPorch + FrontPorch) * 2 / 5 .
// Input Value : usClock --> ADC Clock (IHTotal)
// Output Value : Return _TRUE if not out of range
//--------------------------------------------------
bit CAdjustCheckAdcClockRange(WORD usClock, WORD *delta)
{
*delta = (stModeInfo.IHTotal - stModeInfo.IHWidth - (LWORD)stModeInfo.IHTotal * (LWORD)stModeInfo.IHSyncPulseCount / stModeInfo.IHCount) * 4 / 10;
if((usClock > stModeInfo.IHTotal) && ((usClock - stModeInfo.IHTotal) > *delta))
return _FALSE;
if((usClock <= stModeInfo.IHTotal) && ((stModeInfo.IHTotal - usClock) > *delta))
return _FALSE;
return _TRUE;
}
//--------------------------------------------------
// Description : Set ADC clock (IHTotal)
// Input Value : usClock --> Target ADC clock
// Output Value : None
//--------------------------------------------------
void CAdjustAdcClock(WORD usClock)
{
/*
BYTE mcode, ncode, temp0, temp1;
WORD delta;
CAdjustEnableWatchDog(_WD_DV_TIMEOUT);
if(!CAdjustCheckAdcClockRange(usClock, &delta))
usClock = stModeInfo.IHTotal;
pData[0] = 0x0c;
pData[1] = 0x4f;
pData[2] = 0x24;
pData[3] = 0x00 | _DDS_P_CODE;
CScalerWrite(_PLL_DIV_CTRL_98, 4, pData, _AUTOINC);
#if(_M2PLL_USE == _ON)
pData[0] = ((_APLL1_M_CODE * _RTD_M2PLL_RATIO) - 2);
#else
pData[0] = (_APLL1_M_CODE - 2);
#endif
pData[1] = (_APLL1_N_CODE - 2);
pData[2] = 0x37;
CScalerWrite(_PLL1_M_A1, 3, pData, _AUTOINC);
// usClock * 2 -------------------------------------
usClock = usClock * 2;
//--------------------------------------------------
((WORD *)pData)[2] = 100;
temp1 = 11;
do
{
temp0 = ((LWORD)31 * _APLL1_N_CODE * temp1 * usClock)
/ ((LWORD)32 * _APLL1_M_CODE * stModeInfo.IHCount);
((WORD *)pData)[0] = ((LWORD)3100 * _APLL1_N_CODE * temp1 * usClock)
/ ((LWORD)_APLL1_M_CODE * temp0 * stModeInfo.IHCount);
if(((WORD *)pData)[0] > 3240)
{
((WORD *)pData)[0] = ((WORD *)pData)[0] - 3200;
if(((WORD *)pData)[0] <= ((WORD *)pData)[2])
{
((WORD *)pData)[2] = ((WORD *)pData)[0];
mcode = temp0;
ncode = temp1;
}
((WORD *)pData)[1] = ((LWORD)3100 * _APLL1_N_CODE * temp1 * usClock)
/ ((LWORD)_APLL1_M_CODE * (temp0 + 1) * stModeInfo.IHCount);
((WORD *)pData)[1] = 3200 > ((WORD *)pData)[1] ? 3200 - ((WORD *)pData)[1] : ((WORD *)pData)[1] - 3200;
if(((WORD *)pData)[1] < 40)
{
mcode = temp0 + 1;
ncode = temp1;
break;
}
if(((WORD *)pData)[1] <= ((WORD *)pData)[2])
{
((WORD *)pData)[2] = ((WORD *)pData)[1];
mcode = temp0 + 1;
ncode = temp1;
}
}
else
{
mcode = temp0;
ncode = temp1;
break;
}
}
while(++temp1 < 48);
usClock = (usClock / 2);
#if(_APLL_FAST_LOCK)
if(GET_FIRST_ADCCLOCK())
{
CScalerRead(_PLL2_M_A5, 2, &pData[14], _AUTOINC);
pData[14] = pData[14] + 2; // Old M code
pData[15] = pData[15] + 2; // Old N code
CScalerRead(_PLLDIV_H_A9, 2, &pData[12], _AUTOINC);
((WORD *)pData)[6] = ((((WORD)(pData[12] & 0x0f)) << 8) | pData[13]) + 1;
CScalerSetByte(_FAST_PLL_CTRL_9F, 0x00);
CScalerSetByte(_FAST_PLL_CTRL_9F, 0x07);
CScalerRead(_FAST_PLL_ISUM_A0, 4, pData, _NON_AUTOINC);
((LWORD *)pData)[1] = (LWORD)pData[15] * mcode * (LWORD)((WORD *)pData)[6]; // H Up
((LWORD *)pData)[2] = (LWORD)ncode * pData[14] * usClock; // H Down
((LWORD *)pData)[0] = ((LWORD *)pData)[0] / ((LWORD *)pData)[2] * ((LWORD *)pData)[1];
if(((LWORD *)pData)[2] > ((LWORD *)pData)[1])
((LWORD *)pData)[0] += (LWORD)4294967295 / ((LWORD *)pData)[2] * 16 * (((LWORD *)pData)[2] - ((LWORD *)pData)[1]);
else
((LWORD *)pData)[0] -= (LWORD)4294967295 / ((LWORD *)pData)[2] * 16 * (((LWORD *)pData)[1] - ((LWORD *)pData)[2]);
CScalerSetByte(_FAST_PLL_CTRL_9F, 0x20);
CScalerSetByte(_FAST_PLL_CTRL_9F, 0x22);
CScalerWrite(_FAST_PLL_ISUM_A0, 4, pData, _NON_AUTOINC);
}
#endif
CScalerSetBit(_PLLDIV_H_A9, 0xf0, HIBYTE(usClock - 1) & 0x0f);
CScalerSetByte(_PLLDIV_L_AA, LOBYTE(usClock - 1));
CScalerSetByte(_PLL2_M_A5, mcode - 2);
CScalerSetByte(_PLL2_N_A6, ncode - 2);
// Original Formula : Icp/M2_Code = 0.4 must be constant
// Icp = M2_Code * 4 / 10
// Icp = 2.5u + A7[0]*2.5u + A7[1]*5u + A7[2]*10u + A7[3]*20u + A7[4]*30u (A)
// 2*Icp = 5u + A7[0]*5u + A7[1]*10u + A7[2]*20u + A7[3]*40u + A7[4]*60u (A)
// Calculate the 2*Icp,
pData[5] = (((WORD)mcode * 4 / 10) < 5) ? 0 : ((WORD)mcode * 4 / 10) - 5;
pData[6] = 0x00;
if(pData[5] >= 60)
{
pData[5] -= 60;
pData[6] |= 0x10;
}
if(pData[5] >= 40)
{
pData[5] -= 40;
pData[6] |= 0x08;
}
if(pData[5] >= 20)
{
pData[5] -= 20;
pData[6] |= 0x04;
}
if(pData[5] >= 10)
{
pData[5] -= 10;
pData[6] |= 0x02;
}
if(pData[5] >= 5)
{
pData[5] -= 5;
pData[6] |= 0x01;
}
CScalerSetBit(_PLL2_CRNT_A7, 0xe0, pData[6]);
if(GET_FIRST_ADCCLOCK())
{
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