📄 pxa250.dat
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JTAG Chain description: This section defines the position of components
on the chain so that these components can be accounted for and bypassed
during the programming operation. There are up to 5 devices that can be
handled, and at least one must be the main processor. Specify that a
device is present with the string 'Enabled' or not present with the string
'Disabled'. Each device that is enabled requires a specification for the
number of bits in the JTAG instruction register. The controlling entity,
usually the main processor is identified by the string 'Controller'.
The order of the components is from TDI to TDO. The procedure needs to
know if the device is the last
****************************************************************************
*/
/* TDI --------> */ Enabled 5 Controller Last
Disabled 0 Other More
Disabled 0 Other More
Disabled 0 Other More
Disabled 0 Other More /* TDO ---------> */
/*
****************************************************************************
Additional flash component UNLOCK controls: 4 addition pins can be defined
that would be controlled to UNLOCK a flash memory device that has external
locking pins. Any unused pins should be set to 9999. Specify the signal level
required to UNLOCK the flash. These signals will be reversed to re-lock the
flash after programming.
****************************************************************************
*/
9999 1 /* SPARE */
9999 1 /* SPARE */
9999 1 /* SPARE */
9999 1 /* SPARE */
/*
****************************************************************************
ALIGNMENT CHECKPOINT # 3 - DO NOT MODIFY THIS DATA
****************************************************************************
*/
3333
/*
****************************************************************************
number of flash devices in parallel on the bus
****************************************************************************
*/
2
/*
****************************************************************************
position of nsdcas signal - toggled in parallel with any chip select
****************************************************************************
*/
226 /* nsdcas */
/*
****************************************************************************
Flash programming Mode: WORD or BUFFER
WORD programming is useful for doing things like smoothly crossing device
boundaries but is a little slower.
****************************************************************************
*/
BUFFER /* WORD or BUFFER is the allowed entry */
/*
****************************************************************************
E N D O F D A T A
****************************************************************************
*/
/* Reference information - BSDL file used for this platform
--------------------------------------------------------------------------------
-- File Type: BSDL description for top level entity pxa250_jtag
-- Date Created: June-2002
-- Author: jboyer
-- Revision: B2 v1_1
--------------------------------------------------------------------------------
entity pxa250_jtag is
generic(PHYSICAL_PIN_MAP : string := "MBGA_256");
port ( gpio : inout bit_vector(80 DOWNTO 0);
scl : inout bit;
sda : inout bit;
usb_n : inout bit;
usb_p : inout bit;
mmdat : inout bit;
mmcmd : inout bit;
md : inout bit_vector(31 DOWNTO 0);
pwr_en : buffer bit;
nreset_out : buffer bit;
ac_reset_n : buffer bit;
rdnwr : out bit;
sdclk_0 : buffer bit;
sdclk_1 : out bit;
sdclk_2 : buffer bit;
sdcke : buffer bit_vector(1 DOWNTO 0);
nsdcs_0 : out bit;
nsdcs_1 : buffer bit;
nsdcs_2 : buffer bit;
nsdcs_3 : buffer bit;
dqm_0 : out bit;
dqm_1 : out bit;
dqm_2 : out bit;
dqm_3 : out bit;
nsdcas : out bit;
nsdras : out bit;
nwe : out bit;
noe : out bit;
ncs_0 : out bit;
ma : out bit_vector(25 DOWNTO 0);
test : in bit;
testclk : in bit;
nvdd_fault : in bit;
nbatt_fault : in bit;
boot_sel : in bit_vector(2 DOWNTO 0);
nreset : in bit;
pextal : linkage bit;
textal : linkage bit;
yp : linkage bit;
ym : linkage bit;
xp : linkage bit;
xm : linkage bit;
ref : linkage bit;
pxtal : linkage bit;
txtal : linkage bit;
tms : in bit;
tck : in bit;
tdi : in bit;
tdo : out bit;
ntrst : in bit;
vdd : linkage bit_vector(8 downto 0);
vss : linkage bit_vector(5 downto 0);
vddn : linkage bit_vector(13 downto 0);
vssn : linkage bit_vector(14 downto 0);
pll_vcc : linkage bit;
pll_sense : linkage bit;
vcckp : linkage bit;
adc_vcc : linkage bit;
batt_vcc : linkage bit;
vddq : linkage bit_vector(4 downto 0);
vssq : linkage bit_vector(12 downto 0)
);
use STD_1149_1_1994.all;
attribute COMPONENT_CONFORMANCE of pxa250_jtag : entity is
"STD_1149_1_1993";
attribute PIN_MAP of pxa250_jtag : entity is PHYSICAL_PIN_MAP;
constant MBGA_256 : PIN_MAP_STRING :=
"gpio :(R13,T9,P9,A8,B8,D8,E8,B3,C3,A2,A3," &
"A4,D5,A5,C5,A6,E5,D6,E6,B7,C7," &
"D7,E7,M16,N16,M13,P16,R16,P14,R15,T15," &
"T14,P13,C15,B15,B14,A15,D13,B13,F8,F10," &
"E13,B10,B11,A12,A14,A13,T13,A16,E11,A10," &
"E10,C9,B9,A9,D9,E9,F9,M12,N15,N12," &
"N14,C1,D12,E12,T8,B4,B5,B6,A7,F7," &
"F12,F14,G15,H14,J11,J12,K14,L13,L12,L10)," &
"scl :D11," &
"sda :A11," &
"usb_n :B12," &
"usb_p :C12," &
"mmdat :B16," &
"mmcmd :D14," &
"md :(P12,R11," &
"P10,L8,P8,P7,R7,P6,T3,N1,M2,L4," &
"K3,J4,H5,H3,M10,T12,N10,P11,T11,R9," &
"T10,M9,M7,M6,T7,N6,T6,L5,M5,N4)," &
"pwr_en :L11," &
"nreset_out :K11," &
"ac_reset_n :D10," &
"rdnwr :D3," &
"sdclk_0 :D2," &
"sdclk_1 :F5," &
"sdclk_2 :D1," &
"sdcke :(E3,E4)," &
"nsdcs_0 :F1," &
"nsdcs_1 :G6," &
"nsdcs_2 :G3," &
"nsdcs_3 :F2," &
"dqm_0 :M8," &
"dqm_1 :B1," &
"dqm_2 :B2," &
"dqm_3 :L7," &
"nsdcas :F3," &
"nsdras :E1," &
"nwe :G4," &
"noe :G5," &
"ncs_0 :N8," &
"ma :(P4,T5,P5,R5,T4,R3," &
"P2,R1,P1,N3,M3,M1,L3,L1,K6,K5," &
"K2,K1,J1,J3,J5,J6,H6,H1,H2,G1)," &
"test :G12," &
"testclk :G11," &
"nvdd_fault :K13," &
"nbatt_fault:K12," &
"boot_sel :(F13,G13,G16)," &
"nreset :J13," &
"pextal :K16," &
"textal :L15," &
"yp :D16," &
"ym :E15," &
"xp :E16," &
"xm :F16," &
"ref :F15," &
"pxtal :K15," &
"txtal :L16," &
"tms :H13," &
"tck :H12," &
"tdi :H15," &
"tdo :H16," &
"ntrst :H11," &
"vdd :(L9,L6,K10,K8,J7,H10,G9,G7,F11)," &
"vss :(T1,J9,J8,H9,H8,C16)," &
"vddn :(D4,A1,F4,H4,M14,K4,N11,N13,N7,N9,N5,P3,M4,T16)," &
"vssn :(C2,E2,G2,J2,L2,N2,R2,P15,M15," &
"R14,R12,R10,R8,R6,R4)," &
"pll_vcc :J15," &
"pll_sense :J16," &
"vcckp :T2," &
"adc_vcc :D15," &
"batt_vcc :M11," &
"vddq :(C10,G14,E14,C13,C6)," &
"vssq :(C14,C11,C8,C4,G8,F6,G10,K7,H7,J14,J10,L14,K9)";
attribute TAP_SCAN_IN of tdi : signal is true;
attribute TAP_SCAN_MODE of tms : signal is true;
attribute TAP_SCAN_OUT of tdo : signal is true;
attribute TAP_SCAN_CLOCK of tck : signal is (40.0e6,BOTH);
attribute TAP_SCAN_RESET of ntrst : signal is true;
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