pxa250.dat

很难找到的pxa250的jfalsh烧写所需的配置.dat文件

/* dbpxa250.dat version 1.0
****************************************************************************

    This data file contains the JTAG and board configuration data required 
    for multi-mode JFlash. This data file is a text file with specific 
    format requirements.

    Comment blocks can be defined using the old-style C comment blocks. 
    The difference is that the delimiter characters must have whitespace 
    on both sides. 

    Data may be string data, or numeric. String data is only allowed 
    at specific positions within this file. Numeric data can be decimal, 
    hexadecimal, or octal. 
    Decimal data is assumed, and HEX data may be denoted by a 
    preceding 'X' character.

    Valid HEX data:
        xA0000000
        XA4090000
        Xff

    Valid OCTAL data:
        o765
        O123545

    The data required to fill in this table comes from knowledge of the 
    BSDL file for the processor, the development board user's guide, 
    and specifications for the flash components. 

    Data is position dependent in terms of order. Whitespace is the 
    delimiter for the data and may be used as necessary to keep the 
    data in reasonably readable format. 

    There are checkpoints within this file that are used as validation 
    that the data alignment is correct. DO NOT MODIFY THE CHECKPOINT DATA. 

    The filename of this file is used as the parameter for JFlash. 

/*
****************************************************************************
File Identification strings to display from JFlash  
**************************************************************************** 
*/
    Cotulla     /* Position 0 - Supported Processor Code Name or Number */
    Lubbock     /* Supported Development platform name or number */
    1.0         /* Version number of this data file */
    VL00000001  /* Version lock code for compatibility to JTAG engine */

/*
****************************************************************************
Basic JTAG setup required by JFlash
**************************************************************************** 
*/
    385     /* The number of bits in the Boundary Scan chain */
    5       /* The number of bits in the instruction register */
    X0      /* EXTEST instruction in HEX */
    X7E     /* IDCODE instruction in HEX */
    X7F     /* BYPASS instruction */
/*
****************************************************************************
Chip select offsets: 6 total, beginning with chip select 0 and in order.
**************************************************************************** 
*/
    230  101 164 165 166 119
/*
****************************************************************************
Control Bits required for bus transactions
**************************************************************************** 
*/
    229      /* Output enable: nOE_OUT */
    228      /* Write Enable: nWE_OUT */
    84       /* Memory data upper bit control: mdupper_ctrl */
    85       /* Memory data lower bit control: mdlower_ctrl */
    212      /* Read/Write direction: RD_nWR_OUT */
/*
****************************************************************************
ALIGNMENT CHECKPOINT # 1 - DO NOT MODIFY THIS DATA
**************************************************************************** 
*/
    1111    /* position 20 */
/*
****************************************************************************
Address bit offsets beginning with A0
**************************************************************************** 
*/
    231 232 233 234 235 236 237 238     /* A0 - A7 */   
    239 240 241 242 243 244 245 246     /* A8 - A15 */
    247 248 249 250 251 252 253 254     /* A16 - A23 */
    255 256                             /* A24, A25 */
/*
****************************************************************************
Input data bit offsets beginning with D0
**************************************************************************** 
*/
    344 345 346 347 348 349 350 351     /* D0 -  D7  */
    352 353 354 355 356 357 358 359     /* D8 -  D15 */
    360 361 362 363 364 365 366 367     /* D16 - D23 */
    368 369 370 371 372 373 374 375     /* D24 - D31 */
/*
****************************************************************************
Output data bit offsets beginning with D0
**************************************************************************** 
*/
    173 174 175 176 177 178 179 180     /* D0 -  D7  */
    181 182 183 184 185 186 187 188     /* D8 -  D15 */
    189 190 191 192 193 194 195 196     /* D16 - D23 */
    197 198 199 200 201 202 203 204     /* D24 - D31 */
/*
****************************************************************************
ALIGNMENT CHECKPOINT # 2 - DO NOT MODIFY THIS DATA
**************************************************************************** 
*/
    2222    /* position 111 */
/*
****************************************************************************
Width of data bus. Only 16 or 32 are allowed as values 
**************************************************************************** 
*/
    32
/*
****************************************************************************
Memory Space Definition for chip selects. The memory addresses are defined 
by a lower and upper limit and the chip select that is used to access this
address. The chip selects are identified by an integer.
Only 6 regions are allowed. If there are fewer regions on the platform, 
then specify the unused regions with XFFFFFFFF as the lower and upper 
region limits and specify the highest chip select for these regions.  
**************************************************************************** 
*/
/*  Lower Address       Upper Address       Chip Select */
    X00000000           X02000000           0
    X04000000           X06000000           1
    X08000000           X08000100           2
    X0C000000           X0E100000           3
    X10000000           X10400000           4
    X14000000           X18000000           5
/*
****************************************************************************
Processor JTAG ID string. The upper 4 bits that define the stepping are not
required here, but must be defined afterward to equate the value to the 
named stepping. 
**************************************************************************** 
*/
    1001001001100100    /* Processor ID */ 
    00000001001         /* Intel Manufacturer Code */
    1                   /* required by JTAG Standards */
/*
****************************************************************************
Stepping labels relative to the top 4 bits of the chip ID. 
16 values required. 
**************************************************************************** 
*/
    A0       /* id = 0 , data position 131 */
    A1       /* id = 1 */
    B0       /* id = 2 */
    B1       /* id = 3 */
    B2       /* id = 4 */
    ??       /* id = 5 */
    ??       /* id = 6 */
    ??       /* id = 7 */
    ??       /* id = 8 */
    ??       /* id = 9 */
    ??       /* id = 10 */
    ??       /* id = 11 */
    ??       /* id = 12 */
    ??       /* id = 13 */
    ??       /* id = 14 */
    ??       /* id = 15 */
/*
****************************************************************************
Default High bits. These are pins on the chain that are required to be set 
high by default. This list contains some usual pins, and allows for 20 
arbitrary additional pins to be set. This list as with all lists is required 
to have a fixed number of entries. All entries that are not used should be 
set to 9999 
**************************************************************************** 
*/
    /* Normally high */

    230     /* nCS0_OUT */
    101     /* nCS1_OUT */      15      /* nCS1 control pin */
    164     /* nCS2_OUT */      78      /* nCS2 control pin */
    165     /* nCS3_OUT */      79      /* nCS3 control pin */
    166     /* nCS4_OUT */      80      /* nCS4 control pin */
    119     /* nCS5_OUT */      33      /* nCS5 control pin */
    206     /* nCS0 CTRl */
    229     /* nWE_OUT */
    228     /* nOE_OUT */
    208     /* ma_ctrl - address lines enable */
    205     /* dqm_ctrl - DQM Control */
    84      /* mdlower_ctrl - memory data lower 16 bits */
    85      /* mdupper_ctrl - memory data upper 16 bits */
    207     /* nwe_ctrl */
    207     /* noe_ctrl */
    208     /* sdclk_ctrl */
    218     /* nsdcs_0 */
    219     /* nsdcs_1 */
    227     /* nsdras */
    9999    /* SPARE        */
    380     /* nbatt_fault */
    379     /* nvdd_fault */

    /* Arbitrary Additional Pins */

    209    /* sys enable */
    9999   /* SPARE          */
    220     /* nsdcs_2 */
    221     /* nsdcs_3 */
    52      /* GPIO 52 ctl */
    53      /* GPIO 53 ctl */
    138     /* GPIO 52    */
    139     /* GPIO 53    */
    9999    /* additional */
    9999    /* additional */
    9999    /* additional */
    9999    /* additional */
    9999    /* additional */
    9999    /* additional */
    9999    /* additional */
    9999    /* additional */
    9999    /* additional */
    9999    /* additional */
    9999    /* additional */
    9999    /* additional */
/*
****************************************************************************