📄 host.c
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/////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////
#pragma vector = USART0RX_VECTOR
__interrupt void RXhandler (void)
{
rxdata = U0RXBUF;
RXdone = 1;
if(ENABLE == 0)
{
TRFEnable;
BaudSet(0x01);
OSCsel(0x01);
InitialSettings();
send_cstring("Reader enabled.");
ENABLE = 1;
}
__low_power_mode_off_on_exit();
if(FirstSPIdata)
{
irqOFF;
stopCounter;
asm("mov.w #HostCommands,10(SP)");
// This manipulation of SP is needed so that the control transfers to the
//HostCommand function after the interrupt return
}
} /* RXhandler */
/////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////
void HostCommands ()
{
char *phello;
unsigned char *pbuf, count;
POLLING = 0;
/* main loop, never ends */
while(1)
{
pbuf = &buf[0];
Get_line(pbuf);
put_crlf(); /* finish line */
pbuf = &buf[4];
RXErrorFlag = 0;
if(*pbuf == 0xFF)
{ /* check COM port number */
phello = "TRF7960 EVM \r\n";
send_cstring(phello);
}
else if(*pbuf == 0x10)
{ /* register write (adress:data, adress:data, ...) */
send_cstring("Register write request.\r\n");
count = buf[0] - 8;
WriteSingle(&buf[5], count);
}
else if(*pbuf == 0x11)
{ /* continous write (adress:data, data, ...) */
phello = "Continous write request.\r\n";
send_cstring(phello);
count = buf[0] - 8;
WriteCont(&buf[5], count);
}
else if(*pbuf == 0x12)
{ /* register read (adress:data, adress:data, ...) */
phello = "Register read request.\r\n";
send_cstring(phello);
count = buf[0] - 8;
ReadSingle(&buf[5], count);
Response(&buf[5], count);
}
else if(*pbuf == 0x13)
{ /* continous read (adress:data, data, ...) */
send_cstring("Continous read request\r\n");
pbuf++;
count = *pbuf; /* the amount of registers to be read */
/* is speciffied after the command */
pbuf++;
buf[5] = *pbuf; /* the start register is speciffied */
/* after the amount of registers */
ReadCont(&buf[5], count);
Response(&buf[5], count);
}
else if(*pbuf == 0x14)
{ /* inventory request */
phello = "ISO 15693 Inventory request.\r\n";
send_cstring(phello);
flags = buf[5];
for(count = 0; count < 8; count++) buf[count + 20] = 0x00;
InventoryRequest(&buf[20], 0x00);
}
else if(*pbuf == 0x15)
{ /* direct command */
phello = "Direct command.\r\n";
send_cstring(phello);
DirectCommand(&buf[5]);
}
else if(*pbuf == 0x16)
{ /* raw */
phello = "RAW mode.\r\n";
send_cstring(phello);
count = buf[0] - 8;
RAWwrite(&buf[5], count);
}
else if(*pbuf == 0x18)
{ /* request code */
phello = "Request mode.\r\n";
send_cstring(phello);
count = buf[0] - 8;
RequestCommand(&buf[0], count, 0x00, 0);
}
else if(*pbuf == 0x19)
{ /* testing 14443A - sending and recieving */
/*
* in different bitrates with changing ;
* the ISOmode register after TX
*/
phello = "14443A Request - change bit rate.\r\n";
send_cstring(phello);
count = buf[0] - 9;
Request14443A(&buf[1], count, buf[5]);
}
else if(*pbuf == 0x17)
{ /* request code */
phello = "Request EPC - delayed transmit.\r\n";
send_cstring(phello);
count = buf[0] - 8;
RequestEPC(&buf[0], count);
}
else if(*pbuf == 0x34)
{ /* SID poll */
phello = "Ti SID Poll.\r\n";
send_cstring(phello);
flags = buf[5];
for(count = 0; count < 4; count++) buf[count + 20] = 0x00;
TIInventoryRequest(&buf[20], 0x00);
}
else if(*pbuf == 0x54)
{
phello = "EPC BeginRound.\r\n";
send_cstring(phello);
if(*(pbuf + 1) == 0x01)
count = 0x03;
else
count = 0x00;
BeginRound(0, &buf[100], count);
}
else if(*pbuf == 0x55)
{ /* CSS with delayed Stop condition */
phello = "EPC CSS.\r\n";
send_cstring(phello);
CSScommand();
}
else if(*pbuf == 0x56)
{ /* EPC Begin Rond */
phello = "EPC Delayed command.\r\n";
send_cstring(phello);
count = buf[0] - 8;
RequestEPC(&buf[0], count);
}
else if(*pbuf == 0x0F)
{ /* Direct mode */
phello = "Direct mode.\r\n";
send_cstring(phello);
DirectMode();
}
else if((*pbuf == 0xB0) || (*pbuf == 0xB1))
{ /* 0xB0 - REQB */
phello = "14443B REQB.\r\n"; /* 0xB1 - WUPB */
send_cstring(phello);
AnticollisionSequenceB(*pbuf, *(pbuf + 1));
}
else if((*pbuf == 0xA0) || (*pbuf == 0xA1))
{ /* 0xA0 - REQA */
phello = "14443A REQA.\r\n";
send_cstring(phello);
AnticollisionSequenceA(*(pbuf + 1));
}
else if(*pbuf == 0xA2)
{ /* 0xA0 - REQA */
phello = "14443A Select.\r\n";
send_cstring(phello);
switch(buf[0])
{
case 0x0D:
for(count = 1; count < 6; count++) buf[99 + count] = *(pbuf + count);
break;
case 0x11:
for(count = 1; count < 11; count++) buf[100 + count] = *(pbuf + count);
buf[100] = 0x88;
break;
case 0x15:
for(count = 1; count < 5; count++) buf[100 + count] = *(pbuf + count);
buf[100] = 0x88;
buf[105] = 0x88;
for(count = 1; count < 10; count++) buf[105 + count] = *(pbuf + count + 4);
} /* switch */
buf[0] = ISOControl;
buf[1] = 0x88; /* recieve with no CRC */
WriteSingle(buf, 2);
buf[5] = 0x26; /* send REQA command */
if(RequestCommand(&buf[0], 0x00, 0x0f, 1) == 0)
{
if(SelectCommand(0x93, &buf[100]))
{
if(SelectCommand(0x95, &buf[105])) SelectCommand(0x97, &buf[110]);
}
}
}
else if(*pbuf == 0x03)
{ /* enable or disable the reader chip */
if(*(pbuf + 1) == 0x00)
{
/*
* enable;
* BaudSet(*(pbuf + 1));
* OSCsel(*(pbuf + 1));
* InitialSettings();
* send_cstring("Reader enabled.");
* ENABLE = 1;
*/
}
else if(*(pbuf + 1) == 0xFF)
{
BaudSet(*(pbuf + 1));
OSCsel(*(pbuf + 1));
TRFDisable;
send_cstring("Reader disabled.");
ENABLE = 0;
}
else if(*(pbuf + 1) == 0x0A)
{
BaudSet(0x00);
OSCsel(0x00);
send_cstring("External clock.");
}
else if(*(pbuf + 1) == 0x0B)
{
BaudSet(0x01);
OSCsel(0x01);
send_cstring("Internal clock.");
}
else
{
}
}
else if(*pbuf == 0xF0)
{ /* AGC toggle */
buf[0] = ChipStateControl;
buf[1] = ChipStateControl;
ReadSingle(&buf[1], 1);
if(*(pbuf + 1) == 0xFF)
buf[1] |= BIT2;
else
buf[1] &= ~BIT2;
WriteSingle(buf, 2);
}
else if(*pbuf == 0xF1)
{ /* AM PM toggle */
buf[0] = ChipStateControl;
buf[1] = ChipStateControl;
ReadSingle(&buf[1], 1);
if(*(pbuf + 1) == 0xFF)
buf[1] &= ~BIT3;
else
buf[1] |= BIT3;
WriteSingle(buf, 2);
}
else if(*pbuf == 0xF2)
{ /* Full - half power selection (FF - full power) */
buf[0] = ChipStateControl;
buf[1] = ChipStateControl;
ReadSingle(&buf[1], 1);
if(*(pbuf + 1) == 0xFF)
buf[1] &= ~BIT4;
else
buf[1] |= BIT4;
WriteSingle(buf, 2);
}
else if(*pbuf == 0xFE)
{ /* Firmware Version Number */
phello = "Firmware Version 1.1A \r\n";
send_cstring(phello);
}
else
{
phello = "Unknown command.\r\n";
send_cstring(phello);
} /* end if */
while(!(IFG1 & UTXIFG0));
} /* end while(1) */
} /* HostCommands */
// === Modifications====================================================
// 10/30/06 Aarthi Created a new function HostCommands() - Moved the
// while(1) loop from function main() to HostCommands().
// 10/30/06 Aarthi Added code to ISR RXHandler() to manipulate the Stack
// Pointer to jump to HostCommands() function on receiving
// first SPI data.
// 10/31/06 Aarthi Added code in HostCommands() to return firmware
// version number on querying.
// =====================================================================
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