sjall_timesim.vhd

很好用的7180的驱动

    generic map(
      LOC => "PAD62"
    )
    port map (
      I => din_64_35_IBUF_22,
      O => din_64_35_IBUF_0
    );
  din_64_35_IBUF : X_BUF
    generic map(
      LOC => "PAD62"
    )
    port map (
      I => din_64(35),
      O => din_64_35_IBUF_22
    );
  din_64_43_IMUX : X_BUF
    generic map(
      LOC => "PAD90"
    )
    port map (
      I => din_64_43_IBUF_23,
      O => din_64_43_IBUF_0
    );
  din_64_43_IBUF : X_BUF
    generic map(
      LOC => "PAD90"
    )
    port map (
      I => din_64(43),
      O => din_64_43_IBUF_23
    );
  din_64_51_IMUX : X_BUF
    generic map(
      LOC => "PAD107"
    )
    port map (
      I => din_64_51_IBUF_24,
      O => din_64_51_IBUF_0
    );
  din_64_51_IBUF : X_BUF
    generic map(
      LOC => "PAD107"
    )
    port map (
      I => din_64(51),
      O => din_64_51_IBUF_24
    );
  din_64_58_IMUX : X_BUF
    generic map(
      LOC => "PAD171"
    )
    port map (
      I => din_64_58_IBUF_25,
      O => din_64_58_IBUF_0
    );
  din_64_58_IBUF : X_BUF
    generic map(
      LOC => "PAD171"
    )
    port map (
      I => din_64(58),
      O => din_64_58_IBUF_25
    );
  din_64_59_IMUX : X_BUF
    generic map(
      LOC => "PAD126"
    )
    port map (
      I => din_64_59_IBUF_26,
      O => din_64_59_IBUF_0
    );
  din_64_59_IBUF : X_BUF
    generic map(
      LOC => "PAD126"
    )
    port map (
      I => din_64(59),
      O => din_64_59_IBUF_26
    );
  dout_8_0_OBUF : X_OBUF
    generic map(
      LOC => "PAD157"
    )
    port map (
      I => dout_8_0_OUTMUX_27,
      O => dout_8(0)
    );
  dout_8_0_OUTMUX : X_BUF
    generic map(
      LOC => "PAD157"
    )
    port map (
      I => dout_8_0_OBUF_0,
      O => dout_8_0_OUTMUX_27
    );
  dout_8_1_OBUF : X_OBUF
    generic map(
      LOC => "PAD148"
    )
    port map (
      I => dout_8_1_OUTMUX_28,
      O => dout_8(1)
    );
  dout_8_1_OUTMUX : X_BUF
    generic map(
      LOC => "PAD148"
    )
    port map (
      I => dout_8_1_OBUF_1,
      O => dout_8_1_OUTMUX_28
    );
  dout_8_2_OBUF : X_OBUF
    generic map(
      LOC => "PAD146"
    )
    port map (
      I => dout_8_2_OUTMUX_29,
      O => dout_8(2)
    );
  dout_8_2_OUTMUX : X_BUF
    generic map(
      LOC => "PAD146"
    )
    port map (
      I => dout_8_2_OBUF_2,
      O => dout_8_2_OUTMUX_29
    );
  dout_8_3_OBUF : X_OBUF
    generic map(
      LOC => "PAD145"
    )
    port map (
      I => dout_8_3_OUTMUX_30,
      O => dout_8(3)
    );
  dout_8_3_OUTMUX : X_BUF
    generic map(
      LOC => "PAD145"
    )
    port map (
      I => dout_8_3_OBUF_3,
      O => dout_8_3_OUTMUX_30
    );
  dout_8_4_OBUF : X_OBUF
    generic map(
      LOC => "PAD156"
    )
    port map (
      I => dout_8_4_OUTMUX_31,
      O => dout_8(4)
    );
  dout_8_4_OUTMUX : X_BUF
    generic map(
      LOC => "PAD156"
    )
    port map (
      I => dout_8_4_OBUF_4,
      O => dout_8_4_OUTMUX_31
    );
  dout_8_5_OBUF : X_OBUF
    generic map(
      LOC => "PAD155"
    )
    port map (
      I => dout_8_5_OUTMUX_32,
      O => dout_8(5)
    );
  dout_8_5_OUTMUX : X_BUF
    generic map(
      LOC => "PAD155"
    )
    port map (
      I => dout_8_5_OBUF_5,
      O => dout_8_5_OUTMUX_32
    );
  dout_8_6_OBUF : X_OBUF
    generic map(
      LOC => "PAD151"
    )
    port map (
      I => dout_8_6_OUTMUX_33,
      O => dout_8(6)
    );
  dout_8_6_OUTMUX : X_BUF
    generic map(
      LOC => "PAD151"
    )
    port map (
      I => dout_8_6_OBUF_6,
      O => dout_8_6_OUTMUX_33
    );
  dout_8_7_OBUF : X_OBUF
    generic map(
      LOC => "PAD154"
    )
    port map (
      I => dout_8_7_OUTMUX_34,
      O => dout_8(7)
    );
  dout_8_7_OUTMUX : X_BUF
    generic map(
      LOC => "PAD154"
    )
    port map (
      I => dout_8_7_OBUF_7,
      O => dout_8_7_OUTMUX_34
    );
  XLXI_7_XLXI_26_LOGIC_ZERO : X_ZERO
    generic map(
      LOC => "DLL1"
    )
    port map (
      O => XLXI_7_XLXI_26_LOGIC_ZERO_35
    );
  XLXI_7_XLXI_26 : X_CLKDLLE
    generic map(
      CLKDV_DIVIDE => 2.0000,
      DUTY_CYCLE_CORRECTION => TRUE,
      LOC => "DLL1",
      MAXPERCLKIN => 40000 ps
    )
    port map (
      CLKIN => XLXI_7_XLXN_97,
      CLKFB => XLXI_7_XLXN_75,
      RST => XLXI_7_XLXI_26_LOGIC_ZERO_35,
      CLK0 => XLXI_7_XLXN_76,
      CLK90 => XLXI_7_XLXN_77,
      CLK180 => XLXI_7_XLXI_26_CLK180,
      CLK270 => XLXI_7_XLXI_26_CLK270,
      CLK2X => XLXI_7_XLXI_26_CLK2X,
      CLK2X180 => XLXI_7_XLXI_26_CLK2X180,
      CLKDV => XLXI_7_XLXI_26_CLKDV,
      LOCKED => XLXI_7_XLXI_26_LOCKED
    );
  XLXI_2_BU2_U0_gen_as_fgas_normgen_memblk_bmem_dp_mem_mem1ncr_coreinst_B20_LOGIC_ZERO : X_ZERO
    generic map(
      LOC => "RAMB4_R1C1"
    )
    port map (
      O => XLXI_2_BU2_U0_gen_as_fgas_normgen_memblk_bmem_dp_mem_mem1ncr_coreinst_B20_LOGIC_ZERO_36
    );
  XLXI_2_BU2_U0_gen_as_fgas_normgen_memblk_bmem_dp_mem_mem1ncr_coreinst_B20_LOGIC_ONE : X_ONE
    generic map(
      LOC => "RAMB4_R1C1"
    )
    port map (
      O => XLXI_2_BU2_U0_gen_as_fgas_normgen_memblk_bmem_dp_mem_mem1ncr_coreinst_B20_LOGIC_ONE_37
    );
  XLXI_2_BU2_U0_gen_as_fgas_normgen_memblk_bmem_dp_mem_mem1ncr_coreinst_B20 : X_RAMB4_S2_S16
    generic map(
      INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_07 => X"0000000000000000000000