sjall_timesim.nlf

很好用的7180的驱动

Release 9.1i - netgen J.30
Copyright (c) 1995-2007 Xilinx, Inc.  All rights reserved.

Command Line: netgen -intstyle ise -s 7 -pcf sjall.pcf -rpw 100 -tpw 0 -ar
Structure -tm sjall -w -dir netgen/par -ofmt vhdl -sim sjall.ncd
sjall_timesim.vhd  

Read and Annotate design 'sjall.ncd' ...
Loading device for application Rf_Device from file '2s50e.nph' in environment
C:\Xilinx91i.
   "sjall" is an NCD, version 3.1, device xc2s50e, package tq144, speed -7
Loading constraints from 'sjall.pcf'...
The speed grade (-7) differs from the speed grade specified in the .ncd file
(-7).
The number of routable networks is 310
Flattening design ...
Processing design ... 
  Preping design's networks ...
  Preping design's macros ...
Writing VHDL netlist 'E:\Application\SJ\FPGA\netgen\par\sjall_timesim.vhd' ...
Writing VHDL SDF file 'E:\Application\SJ\FPGA\netgen\par\sjall_timesim.sdf' ...
INFO:NetListWriters:635 - The generated VHDL netlist contains Xilinx SIMPRIM
   simulation primitives and has to be used with SIMPRIM library for correct
   compilation and simulation. 
Number of warnings: 0
Number of info messages: 1
Total memory usage is 102044 kilobytes