_synthesis.nlf

很好用的7180的驱动

Release 9.1i - netgen J.30
Copyright (c) 1995-2007 Xilinx, Inc.  All rights reserved.

Command Line: netgen -intstyle ise -ar Structure -tm sjall -w -dir
netgen/synthesis -ofmt vhdl -sim sjall.ngc _synthesis.vhd  

Reading design 'sjall.ngc' ...
Flattening design ...
Processing design ... 
  Preping design's networks ...
  Preping design's macros ...
Writing VHDL netlist 'E:\Application\SJ\FPGA\netgen\synthesis\_synthesis.vhd'
...
INFO:NetListWriters:635 - The generated VHDL netlist contains Xilinx UNISIM
   simulation primitives and has to be used with UNISIM library for correct
   compilation and simulation. 
Number of warnings: 0
Number of info messages: 1
Total memory usage is 66368 kilobytes