_synthesis.vhd

很好用的7180的驱动

--------------------------------------------------------------------------------
-- Copyright (c) 1995-2007 Xilinx, Inc.  All rights reserved.
--------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor: Xilinx
-- \   \   \/     Version: J.30
--  \   \         Application: netgen
--  /   /         Filename: _synthesis.vhd
-- /___/   /\     Timestamp: Tue Jul 08 20:33:35 2008
-- \   \  /  \ 
--  \___\/\___\
--             
-- Command	: -intstyle ise -ar Structure -tm sjall -w -dir netgen/synthesis -ofmt vhdl -sim sjall.ngc _synthesis.vhd 
-- Device	: xc2s50e-7-tq144
-- Input file	: sjall.ngc
-- Output file	: E:\Application\SJ\FPGA\netgen\synthesis\_synthesis.vhd
-- # of Entities	: 1
-- Design Name	: sjall
-- Xilinx	: C:\Xilinx91i
--             
-- Purpose:    
--     This VHDL netlist is a verification model and uses simulation 
--     primitives which may not represent the true implementation of the 
--     device, however the netlist is functionally correct and should not 
--     be modified. This file cannot be synthesized and should only be used 
--     with supported simulation tools.
--             
-- Reference:  
--     Development System Reference Guide, Chapter 23
--     Synthesis and Simulation Design Guide, Chapter 6
--             
--------------------------------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;

entity sjall is
  port (
    vsync : out STD_LOGIC; 
    wr_en : in STD_LOGIC := 'X'; 
    href : out STD_LOGIC; 
    clk_40 : in STD_LOGIC := 'X'; 
    vref : out STD_LOGIC; 
    clk_27M : in STD_LOGIC := 'X'; 
    cblank : out STD_LOGIC; 
    wr_133 : in STD_LOGIC := 'X'; 
    hsync : out STD_LOGIC; 
    rd_27clk : in STD_LOGIC := 'X'; 
    dout_8 : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
    din_64 : in STD_LOGIC_VECTOR ( 63 downto 0 ) 
  );
end sjall;

architecture Structure of sjall is
  component FIFO
    port (
      rd_en : in STD_LOGIC := 'X'; 
      wr_en : in STD_LOGIC := 'X'; 
      full : out STD_LOGIC; 
      empty : out STD_LOGIC; 
      wr_clk : in STD_LOGIC := 'X'; 
      rst : in STD_LOGIC := 'X'; 
      rd_clk : in STD_LOGIC := 'X'; 
      dout : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
      din : in STD_LOGIC_VECTOR ( 63 downto 0 ) 
    );
  end component;
  signal vsync_OBUF_0 : STD_LOGIC; 
  signal wr_en_IBUF_1 : STD_LOGIC; 
  signal href_OBUF_2 : STD_LOGIC; 
  signal clk_40_BUFGP_3 : STD_LOGIC; 
  signal vref_OBUF_4 : STD_LOGIC; 
  signal cblank_OBUF_5 : STD_LOGIC; 
  signal wr_133_BUFGP_6 : STD_LOGIC; 
  signal hsync_OBUF_7 : STD_LOGIC; 
  signal rd_27clk_BUFGP_8 : STD_LOGIC; 
  signal XLXN_29 : STD_LOGIC; 
  signal XLXN_91 : STD_LOGIC; 
  signal XLXN_94 : STD_LOGIC; 
  signal dout_8_7_OBUF_9 : STD_LOGIC; 
  signal dout_8_6_OBUF_10 : STD_LOGIC; 
  signal dout_8_5_OBUF_11 : STD_LOGIC; 
  signal dout_8_4_OBUF_12 : STD_LOGIC; 
  signal dout_8_3_OBUF_13 : STD_LOGIC; 
  signal dout_8_2_OBUF_14 : STD_LOGIC; 
  signal dout_8_1_OBUF_15 : STD_LOGIC; 
  signal dout_8_0_OBUF_16 : STD_LOGIC; 
  signal din_64_63_IBUF_17 : STD_LOGIC; 
  signal din_64_62_IBUF_18 : STD_LOGIC; 
  signal din_64_61_IBUF_19 : STD_LOGIC; 
  signal din_64_60_IBUF_20 : STD_LOGIC; 
  signal din_64_59_IBUF_21 : STD_LOGIC; 
  signal din_64_58_IBUF_22 : STD_LOGIC; 
  signal din_64_57_IBUF_23 : STD_LOGIC; 
  signal din_64_56_IBUF_24 : STD_LOGIC; 
  signal din_64_55_IBUF_25 : STD_LOGIC; 
  signal din_64_54_IBUF_26 : STD_LOGIC; 
  signal din_64_53_IBUF_27 : STD_LOGIC; 
  signal din_64_52_IBUF_28 : STD_LOGIC; 
  signal din_64_51_IBUF_29 : STD_LOGIC; 
  signal din_64_50_IBUF_30 : STD_LOGIC; 
  signal din_64_49_IBUF_31 : STD_LOGIC; 
  signal din_64_48_IBUF_32 : STD_LOGIC; 
  signal din_64_47_IBUF_33 : STD_LOGIC; 
  signal din_64_46_IBUF_34 : STD_LOGIC; 
  signal din_64_45_IBUF_35 : STD_LOGIC; 
  signal din_64_44_IBUF_36 : STD_LOGIC; 
  signal din_64_43_IBUF_37 : STD_LOGIC; 
  signal din_64_42_IBUF_38 : STD_LOGIC; 
  signal din_64_41_IBUF_39 : STD_LOGIC; 
  signal din_64_40_IBUF_40 : STD_LOGIC; 
  signal din_64_39_IBUF_41 : STD_LOGIC; 
  signal din_64_38_IBUF_42 : STD_LOGIC; 
  signal din_64_37_IBUF_43 : STD_LOGIC; 
  signal din_64_36_IBUF_44 : STD_LOGIC; 
  signal din_64_35_IBUF_45 : STD_LOGIC; 
  signal din_64_34_IBUF_46 : STD_LOGIC; 
  signal din_64_33_IBUF_47 : STD_LOGIC; 
  signal din_64_32_IBUF_48 : STD_LOGIC; 
  signal din_64_31_IBUF_49 : STD_LOGIC; 
  signal din_64_30_IBUF_50 : STD_LOGIC; 
  signal din_64_29_IBUF_51 : STD_LOGIC; 
  signal din_64_28_IBUF_52 : STD_LOGIC; 
  signal din_64_27_IBUF_53 : STD_LOGIC; 
  signal din_64_26_IBUF_54 : STD_LOGIC; 
  signal din_64_25_IBUF_55 : STD_LOGIC; 
  signal din_64_24_IBUF_56 : STD_LOGIC; 
  signal din_64_23_IBUF_57 : STD_LOGIC; 
  signal din_64_22_IBUF_58 : STD_LOGIC; 
  signal din_64_21_IBUF_59 : STD_LOGIC; 
  signal din_64_20_IBUF_60 : STD_LOGIC; 
  signal din_64_19_IBUF_61 : STD_LOGIC; 
  signal din_64_18_IBUF_62 : STD_LOGIC; 
  signal din_64_17_IBUF_63 : STD_LOGIC; 
  signal din_64_16_IBUF_64 : STD_LOGIC; 
  signal din_64_15_IBUF_65 : STD_LOGIC; 
  signal din_64_14_IBUF_66 : STD_LOGIC; 
  signal din_64_13_IBUF_67 : STD_LOGIC; 
  signal din_64_12_IBUF_68 : STD_LOGIC; 
  signal din_64_11_IBUF_69 : STD_LOGIC; 
  signal din_64_10_IBUF_70 : STD_LOGIC; 
  signal din_64_9_IBUF_71 : STD_LOGIC; 
  signal din_64_8_IBUF_72 : STD_LOGIC; 
  signal din_64_7_IBUF_73 : STD_LOGIC; 
  signal din_64_6_IBUF_74 : STD_LOGIC; 
  signal din_64_5_IBUF_75 : STD_LOGIC; 
  signal din_64_4_IBUF_76 : STD_LOGIC; 
  signal din_64_3_IBUF_77 : STD_LOGIC; 
  signal din_64_2_IBUF_78 : STD_LOGIC; 
  signal din_64_1_IBUF_79 : STD_LOGIC; 
  signal din_64_0_IBUF_80 : STD_LOGIC; 
  signal N3 : STD_LOGIC; 
  signal XLXI_7_XLXN_97 : STD_LOGIC; 
  signal XLXI_7_XLXN_77 : STD_LOGIC; 
  signal XLXI_7_XLXN_76 : STD_LOGIC; 
  signal XLXI_7_XLXN_75 : STD_LOGIC; 
  signal XLXI_7_XLXN_70 : STD_LOGIC; 
  signal XLXI_3_XLXN_453 : STD_LOGIC; 
  signal XLXI_3_XLXN_452 : STD_LOGIC; 
  signal XLXI_3_XLXN_8 : STD_LOGIC; 
  signal XLXI_3_XLXN_6 : STD_LOGIC; 
  signal XLXI_3_XLXN_4 : STD_LOGIC; 
  signal XLXI_3_XLXN_2 : STD_LOGIC; 
  signal XLXI_3_XLXN_265 : STD_LOGIC; 
  signal XLXI_3_XLXN_260 : STD_LOGIC; 
  signal XLXI_3_XLXN_252 : STD_LOGIC; 
  signal XLXI_3_XLXN_251 : STD_LOGIC; 
  signal XLXI_3_XLXN_242 : STD_LOGIC; 
  signal XLXI_3_XLXN_241 : STD_LOGIC; 
  signal XLXI_3_XLXN_228 : STD_LOGIC; 
  signal XLXI_3_XLXN_227 : STD_LOGIC; 
  signal XLXI_3_XLXN_219 : STD_LOGIC; 
  signal XLXI_3_XLXN_224 : STD_LOGIC; 
  signal XLXI_3_XLXN_223 : STD_LOGIC; 
  signal XLXI_3_XLXN_221 : STD_LOGIC; 
  signal XLXI_3_XLXN_220 : STD_LOGIC; 
  signal XLXI_3_XLXN_154 : STD_LOGIC; 
  signal XLXI_3_XLXN_148 : STD_LOGIC; 
  signal XLXI_3_XLXN_147 : STD_LOGIC; 
  signal XLXI_3_XLXN_152 : STD_LOGIC; 
  signal XLXI_3_XLXN_146 : STD_LOGIC; 
  signal XLXI_3_XLXN_151 : STD_LOGIC; 
  signal XLXI_3_XLXN_150 : STD_LOGIC; 
  signal XLXI_3_XLXN_139 : STD_LOGIC; 
  signal XLXI_3_XLXN_144 : STD_LOGIC; 
  signal XLXI_3_XLXN_137 : STD_LOGIC; 
  signal XLXI_3_XLXN_142 : STD_LOGIC; 
  signal XLXI_3_XLXN_141 : STD_LOGIC; 
  signal XLXI_3_XLXN_140 : STD_LOGIC; 
  signal XLXI_3_XLXN_87 : STD_LOGIC; 
  signal XLXI_3_XLXN_49 : STD_LOGIC; 
  signal XLXI_3_XLXN_48 : STD_LOGIC; 
  signal XLXI_3_XLXN_51 : STD_LOGIC; 
  signal XLXI_3_XLXN_39 : STD_LOGIC; 
  signal XLXI_3_XLXN_38 : STD_LOGIC; 
  signal XLXI_3_XLXN_40 : STD_LOGIC; 
  signal XLXI_3_XLXN_24 : STD_LOGIC; 
  signal XLXI_3_XLXN_23 : STD_LOGIC; 
  signal XLXI_3_XLXN_22 : STD_LOGIC; 
  signal XLXI_3_XLXN_21 : STD_LOGIC; 
  signal XLXI_3_XLXN_12 : STD_LOGIC; 
  signal XLXI_3_XLXN_11 : STD_LOGIC; 
  signal XLXI_3_XLXN_10 : STD_LOGIC; 
  signal XLXI_3_XLXN_595 : STD_LOGIC; 
  signal XLXI_3_XLXN_593 : STD_LOGIC; 
  signal XLXI_3_XLXN_578 : STD_LOGIC; 
  signal XLXI_3_XLXN_581 : STD_LOGIC; 
  signal XLXI_3_XLXN_580 : STD_LOGIC; 
  signal XLXI_3_XLXN_602 : STD_LOGIC; 
  signal XLXI_3_XLXN_601 : STD_LOGIC; 
  signal XLXI_3_XLXN_600 : STD_LOGIC; 
  signal XLXI_3_XLXN_478 : STD_LOGIC; 
  signal XLXI_3_CLK : STD_LOGIC; 
  signal XLXI_3_XLXN_469 : STD_LOGIC; 
  signal XLXI_3_XLXN_466 : STD_LOGIC; 
  signal XLXI_3_XLXN_465 : STD_LOGIC; 
  signal XLXI_3_XLXN_470 : STD_LOGIC; 
  signal XLXI_3_XLXI_1_N0 : STD_LOGIC; 
  signal XLXI_3_XLXI_1_XLXN_1 : STD_LOGIC; 
  signal XLXI_3_XLXI_1_T3 : STD_LOGIC; 
  signal XLXI_3_XLXI_1_T2 : STD_LOGIC; 
  signal XLXI_3_XLXI_1_CEO : STD_LOGIC; 
  signal XLXI_3_XLXI_1_TC : STD_LOGIC; 
  signal XLXI_3_XLXI_1_Q3 : STD_LOGIC; 
  signal XLXI_3_XLXI_1_Q2 : STD_LOGIC; 
  signal XLXI_3_XLXI_1_I_Q3_N1 : STD_LOGIC; 
  signal XLXI_3_XLXI_1_I_Q3_N0 : STD_LOGIC; 
  signal XLXI_3_XLXI_1_I_Q3_TQ : STD_LOGIC; 
  signal XLXI_3_XLXI_1_I_Q2_N1 : STD_LOGIC; 
  signal XLXI_3_XLXI_1_I_Q2_N0 : STD_LOGIC; 
  signal XLXI_3_XLXI_1_I_Q2_TQ : STD_LOGIC; 
  signal XLXI_3_XLXI_1_I_Q1_N1 : STD_LOGIC; 
  signal XLXI_3_XLXI_1_I_Q1_N0 : STD_LOGIC; 
  signal XLXI_3_XLXI_1_I_Q1_TQ : STD_LOGIC; 
  signal XLXI_3_XLXI_1_I_Q0_N1 : STD_LOGIC; 
  signal XLXI_3_XLXI_1_I_Q0_N0 : STD_LOGIC; 
  signal XLXI_3_XLXI_1_I_Q0_TQ : STD_LOGIC; 
  signal XLXI_3_XLXI_3_N0 : STD_LOGIC; 
  signal XLXI_3_XLXI_3_XLXN_1 : STD_LOGIC; 
  signal XLXI_3_XLXI_3_T3 : STD_LOGIC; 
  signal XLXI_3_XLXI_3_T2 : STD_LOGIC; 
  signal XLXI_3_XLXI_3_CEO : STD_LOGIC; 
  signal XLXI_3_XLXI_3_I_Q3_N1 : STD_LOGIC; 
  signal XLXI_3_XLXI_3_I_Q3_N0 : STD_LOGIC; 
  signal XLXI_3_XLXI_3_I_Q3_TQ : STD_LOGIC; 
  signal XLXI_3_XLXI_3_I_Q2_N1 : STD_LOGIC; 
  signal XLXI_3_XLXI_3_I_Q2_N0 : STD_LOGIC; 
  signal XLXI_3_XLXI_3_I_Q2_TQ : STD_LOGIC; 
  signal XLXI_3_XLXI_3_I_Q1_N1 : STD_LOGIC; 
  signal XLXI_3_XLXI_3_I_Q1_N0 : STD_LOGIC; 
  signal XLXI_3_XLXI_3_I_Q1_TQ : STD_LOGIC; 
  signal XLXI_3_XLXI_3_I_Q0_N1 : STD_LOGIC; 
  signal XLXI_3_XLXI_3_I_Q0_N0 : STD_LOGIC; 
  signal XLXI_3_XLXI_3_I_Q0_TQ : STD_LOGIC; 
  signal XLXI_3_XLXI_5_N0 : STD_LOGIC; 
  signal XLXI_3_XLXI_5_XLXN_1 : STD_LOGIC; 
  signal XLXI_3_XLXI_5_T3 : STD_LOGIC; 
  signal XLXI_3_XLXI_5_T2 : STD_LOGIC; 
  signal XLXI_3_XLXI_5_CEO : STD_LOGIC; 
  signal XLXI_3_XLXI_5_I_Q3_N1 : STD_LOGIC; 
  signal XLXI_3_XLXI_5_I_Q3_N0 : STD_LOGIC; 
  signal XLXI_3_XLXI_5_I_Q3_TQ : STD_LOGIC; 
  signal XLXI_3_XLXI_5_I_Q2_N1 : STD_LOGIC; 
  signal XLXI_3_XLXI_5_I_Q2_N0 : STD_LOGIC; 
  signal XLXI_3_XLXI_5_I_Q2_TQ : STD_LOGIC; 
  signal XLXI_3_XLXI_5_I_Q1_N1 : STD_LOGIC; 
  signal XLXI_3_XLXI_5_I_Q1_N0 : STD_LOGIC; 
  signal XLXI_3_XLXI_5_I_Q1_TQ : STD_LOGIC; 
  signal XLXI_3_XLXI_5_I_Q0_N1 : STD_LOGIC; 
  signal XLXI_3_XLXI_5_I_Q0_N0 : STD_LOGIC; 
  signal XLXI_3_XLXI_5_I_Q0_TQ : STD_LOGIC; 
  signal XLXI_3_XLXI_6_N0 : STD_LOGIC; 
  signal XLXI_3_XLXI_6_XLXN_1 : STD_LOGIC; 
  signal XLXI_3_XLXI_6_T3 : STD_LOGIC; 
  signal XLXI_3_XLXI_6_T2 : STD_LOGIC; 
  signal XLXI_3_XLXI_6_CEO : STD_LOGIC; 
  signal XLXI_3_XLXI_6_I_Q3_N1 : STD_LOGIC; 
  signal XLXI_3_XLXI_6_I_Q3_N0 : STD_LOGIC; 
  signal XLXI_3_XLXI_6_I_Q3_TQ : STD_LOGIC; 
  signal XLXI_3_XLXI_6_I_Q2_N1 : STD_LOGIC; 
  signal XLXI_3_XLXI_6_I_Q2_N0 : STD_LOGIC; 
  signal XLXI_3_XLXI_6_I_Q2_TQ : STD_LOGIC; 
  signal XLXI_3_XLXI_6_I_Q1_N1 : STD_LOGIC; 
  signal XLXI_3_XLXI_6_I_Q1_N0 : STD_LOGIC; 
  signal XLXI_3_XLXI_6_I_Q1_TQ : STD_LOGIC; 
  signal XLXI_3_XLXI_6_I_Q0_N1 : STD_LOGIC; 
  signal XLXI_3_XLXI_6_I_Q0_N0 : STD_LOGIC; 
  signal XLXI_3_XLXI_6_I_Q0_TQ : STD_LOGIC; 
  signal XLXI_3_XLXI_7_N0 : STD_LOGIC; 
  signal XLXI_3_XLXI_7_XLXN_1 : STD_LOGIC; 
  signal XLXI_3_XLXI_7_T3 : STD_LOGIC; 
  signal XLXI_3_XLXI_7_T2 : STD_LOGIC; 
  signal XLXI_3_XLXI_7_CEO : STD_LOGIC; 
  signal XLXI_3_XLXI_7_TC : STD_LOGIC; 
  signal XLXI_3_XLXI_7_Q3 : STD_LOGIC; 
  signal XLXI_3_XLXI_7_Q2 : STD_LOGIC; 
  signal XLXI_3_XLXI_7_I_Q3_N1 : STD_LOGIC; 
  signal XLXI_3_XLXI_7_I_Q3_N0 : STD_LOGIC; 
  signal XLXI_3_XLXI_7_I_Q3_TQ : STD_LOGIC; 
  signal XLXI_3_XLXI_7_I_Q2_N1 : STD_LOGIC; 
  signal XLXI_3_XLXI_7_I_Q2_N0 : STD_LOGIC; 
  signal XLXI_3_XLXI_7_I_Q2_TQ : STD_LOGIC; 
  signal XLXI_3_XLXI_7_I_Q1_N1 : STD_LOGIC; 
  signal XLXI_3_XLXI_7_I_Q1_N0 : STD_LOGIC; 
  signal XLXI_3_XLXI_7_I_Q1_TQ : STD_LOGIC; 
  signal XLXI_3_XLXI_7_I_Q0_N1 : STD_LOGIC; 
  signal XLXI_3_XLXI_7_I_Q0_N0 : STD_LOGIC; 
  signal XLXI_3_XLXI_7_I_Q0_TQ : STD_LOGIC; 
  signal XLXI_3_XLXI_219_N0 : STD_LOGIC; 
  signal XLXI_3_XLXI_219_XLXN_1 : STD_LOGIC; 
  signal XLXI_3_XLXI_219_T3 : STD_LOGIC; 
  signal XLXI_3_XLXI_219_T2 : STD_LOGIC; 
  signal XLXI_3_XLXI_219_CEO : STD_LOGIC; 
  signal XLXI_3_XLXI_219_I_Q3_N1 : STD_LOGIC; 
  signal XLXI_3_XLXI_219_I_Q3_N0 : STD_LOGIC; 
  signal XLXI_3_XLXI_219_I_Q3_TQ : STD_LOGIC; 
  signal XLXI_3_XLXI_219_I_Q2_N1 : STD_LOGIC; 
  signal XLXI_3_XLXI_219_I_Q2_N0 : STD_LOGIC; 
  signal XLXI_3_XLXI_219_I_Q2_TQ : STD_LOGIC; 
  signal XLXI_3_XLXI_219_I_Q1_N1 : STD_LOGIC; 
  signal XLXI_3_XLXI_219_I_Q1_N0 : STD_LOGIC; 
  signal XLXI_3_XLXI_219_I_Q1_TQ : STD_LOGIC; 
  signal XLXI_3_XLXI_219_I_Q0_N1 : STD_LOGIC; 
  signal XLXI_3_XLXI_219_I_Q0_N0 : STD_LOGIC; 
  signal XLXI_3_XLXI_219_I_Q0_TQ : STD_LOGIC; 
  signal XLXI_3_XLXI_224_N0 : STD_LOGIC; 
  signal XLXI_3_XLXI_224_dummy : STD_LOGIC; 
  signal XLXI_3_XLXI_224_S1 : STD_LOGIC; 
  signal XLXI_3_XLXI_224_S0 : STD_LOGIC; 
  signal XLXI_3_XLXI_225_N0 : STD_LOGIC; 
  signal XLXI_3_XLXI_225_dummy : STD_LOGIC; 
  signal XLXI_3_XLXI_225_S1 : STD_LOGIC; 
  signal XLXI_3_XLXI_225_S0 : STD_LOGIC; 
  signal XLXI_3_XLXI_112_N1 : STD_LOGIC; 
  signal XLXI_3_XLXI_112_N0 : STD_LOGIC; 
  signal XLXI_3_XLXI_112_A2 : STD_LOGIC; 
  signal XLXI_3_XLXI_112_A1 : STD_LOGIC; 
  signal XLXI_3_XLXI_112_A0 : STD_LOGIC; 
  signal XLXI_3_XLXI_112_AD : STD_LOGIC; 
  signal XLXI_3_XLXI_113_N1 : STD_LOGIC; 
  signal XLXI_3_XLXI_113_N0 : STD_LOGIC; 
  signal XLXI_3_XLXI_113_A2 : STD_LOGIC; 
  signal XLXI_3_XLXI_113_A1 : STD_LOGIC; 
  signal XLXI_3_XLXI_113_A0 : STD_LOGIC; 
  signal XLXI_3_XLXI_113_AD : STD_LOGIC; 
  signal XLXI_3_XLXI_56_N0 : STD_LOGIC; 
  signal XLXI_3_XLXI_56_dummy : STD_LOGIC; 
  signal XLXI_3_XLXI_56_I35 : STD_LOGIC; 
  signal XLXI_3_XLXI_57_N0 : STD_LOGIC; 
  signal XLXI_3_XLXI_57_dummy : STD_LOGIC; 
  signal XLXI_3_XLXI_57_I35 : STD_LOGIC; 
  signal XLXI_3_XLXI_94_N0 : STD_LOGIC; 
  signal XLXI_3_XLXI_94_dummy : STD_LOGIC; 
  signal XLXI_3_XLXI_94_I35 : STD_LOGIC; 
  signal NLW_XLXI_7_XLXI_26_CLK180_UNCONNECTED : STD_LOGIC; 
  signal NLW_XLXI_7_XLXI_26_CLK270_UNCONNECTED : STD_LOGIC; 
  signal NLW_XLXI_7_XLXI_26_CLK2X_UNCONNECTED : STD_LOGIC; 
  signal NLW_XLXI_7_XLXI_26_CLK2X180_UNCONNECTED : STD_LOGIC; 
  signal NLW_XLXI_7_XLXI_26_CLKDV_UNCONNECTED : STD_LOGIC; 
  signal NLW_XLXI_7_XLXI_26_LOCKED_UNCONNECTED : STD_LOGIC; 
  signal NLW_XLXI_2_full_UNCONNECTED : STD_LOGIC; 
  signal NLW_XLXI_2_empty_UNCONNECTED : STD_LOGIC; 
begin
  XST_VCC : VCC
    port map (
      P => N3
    );
  XLXI_13 : IBUF
    port map (
      I => XLXN_94,
      O => XLXN_91
    );
  XLXI_7_XLXI_36 : IBUFG
    port map (
      I => clk_27M,
      O => XLXI_7_XLXN_97
    );
  XLXI_7_XLXI_28 : OBUF
    port map (
      I => XLXI_7_XLXN_77,
      O => XLXN_94
    );
  XLXI_7_XLXI_27 : BUFG
    port map (
      I => XLXI_7_XLXN_76,
      O => XLXI_7_XLXN_75
    );
  XLXI_7_XLXI_26 : CLKDLLE
    generic map(
      CLKDV_DIVIDE => 2.0000,
      DUTY_CYCLE_CORRECTION => TRUE
    )
    port map (
      CLKIN => XLXI_7_XLXN_97,
      CLKFB => XLXI_7_XLXN_75,
      RST => XLXI_7_XLXN_70,
      CLK0 => XLXI_7_XLXN_76,
      CLK90 => XLXI_7_XLXN_77,
      CLK180 => NLW_XLXI_7_XLXI_26_CLK180_UNCONNECTED,
      CLK270 => NLW_XLXI_7_XLXI_26_CLK270_UNCONNECTED,
      CLK2X => NLW_XLXI_7_XLXI_26_CLK2X_UNCONNECTED,
      CLK2X180 => NLW_XLXI_7_XLXI_26_CLK2X180_UNCONNECTED,
      CLKDV => NLW_XLXI_7_XLXI_26_CLKDV_UNCONNECTED,
      LOCKED => NLW_XLXI_7_XLXI_26_LOCKED_UNCONNECTED
    );
  XLXI_7_XLXI_24 : GND
    port map (
      G => XLXI_7_XLXN_70
    );
  XLXI_3_XLXI_249 : INV
    port map (
      I => XLXI_3_XLXN_600,
      O => vsync_OBUF_0
    );
  XLXI_3_XLXI_246 : OR2
    port map (
      I0 => XLXI_3_XLXN_593,
      I1 => XLXI_3_XLXN_578,
      O => XLXI_3_XLXN_595
    );
  XLXI_3_XLXI_245 : AND2
    port map (
      I0 => XLXI_3_XLXN_470,
      I1 => XLXI_3_XLXN_469,
      O => XLXI_3_XLXN_593
    );
  XLXI_3_XLXI_243 : NAND2
    port map (
      I0 => XLXI_3_XLXN_453,
      I1 => XLXI_3_XLXN_452,
      O => hsync_OBUF_7
    );
  XLXI_3_XLXI_240 : OR2
    port map (
      I0 => XLXI_3_XLXN_251,
      I1 => XLXI_3_XLXN_144,
      O => XLXI_3_XLXN_146
    );
  XLXI_3_XLXI_235 : AND2
    port map (
      I0 => XLXI_3_XLXN_139,
      I1 => XLXI_3_XLXN_140,
      O => XLXI_3_XLXN_144
    );
  XLXI_3_XLXI_234 : AND2
    port map (
      I0 => XLXI_3_XLXN_142,
      I1 => XLXI_3_XLXN_141,
      O => XLXI_3_XLXN_251
    );
  XLXI_3_XLXI_233 : AND2
    port map (
      I0 => XLXI_3_XLXN_228,
      I1 => XLXI_3_XLXN_227,
      O => XLXI_3_XLXN_252
    );
  XLXI_3_XLXI_232 : OR2
    port map (
      I0 => XLXI_3_XLXN_252,
      I1 => clk_40_BUFGP_3,
      O => XLXI_3_XLXN_265
    );
  XLXI_3_XLXI_231 : OR2
    port map (
      I0 => XLXI_3_XLXN_251,
      I1 => clk_40_BUFGP_3,
      O => XLXI_3_XLXN_260
    );
  XLXI_3_XLXI_230 : NOR2
    port map (
      I0 => XLXI_3_XLXN_242,
      I1 => XLXI_3_XLXN_241,
      O => cblank_OBUF_5
    );
  XLXI_3_XLXI_229 : INV
    port map (
      I => XLXI_3_XLXN_241,
      O => XLXN_29
    );
  XLXI_3_XLXI_223 : AND2
    port map (
      I0 => XLXI_3_XLXN_137,
      I1 => XLXI_3_XLXN_38,
      O => XLXI_3_XLXN_469
    );
  XLXI_3_XLXI_222 : AND2
    port map (
      I0 => XLXI_3_XLXN_39,
      I1 => XLXI_3_XLXN_48,
      O => XLXI_3_XLXN_465
    );
  XLXI_3_XLXI_111 : OR2
    port map (
      I0 => XLXI_3_XLXN_221,
      I1 => vref_OBUF_4,
      O => XLXI_3_XLXN_580
    );
  XLXI_3_XLXI_107 : AND2
    port map (
      I0 => XLXI_3_XLXN_224,
      I1 => XLXI_3_XLXN_223,
      O => XLXI_3_XLXN_581
    );
  XLXI_3_XLXI_106 : AND2
    port map (
      I0 => XLXI_3_XLXN_220,
      I1 => XLXI_3_XLXN_219,
      O => XLXI_3_XLXN_221
    );
  XLXI_3_XLXI_105 : AND2
    port map (
      I0 => XLXI_3_XLXN_602,
      I1 => XLXI_3_XLXN_601,
      O => vref_OBUF_4
    );
  XLXI_3_XLXI_104 : AND5
    port map (
      I0 => XLXI_3_XLXN_154,
      I1 => XLXI_3_XLXN_150,
      I2 => XLXI_3_XLXN_148,
      I3 => XLXI_3_XLXN_24,
      I4 => XLXI_3_XLXN_23,
      O => XLXI_3_XLXN_219
    );
  XLXI_3_XLXI_103 : NOR5
    port map (
      I0 => XLXI_3_XLXN_152,
      I1 => XLXI_3_XLXN_151,
      I2 => XLXI_3_XLXN_147,
      I3 => XLXI_3_XLXN_22,
      I4 => XLXI_3_XLXN_21,
      O => XLXI_3_XLXN_220
    );
  XLXI_3_XLXI_96 : NOR5
    port map (
      I0 => XLXI_3_XLXN_22,
      I1 => XLXI_3_XLXN_23,
      I2 => XLXI_3_XLXN_24,
      I3 => XLXI_3_XLXN_151,
      I4 => XLXI_3_XLXN_152,
      O => XLXI_3_XLXN_228
    );
  XLXI_3_XLXI_92 : AND5
    port map (
      I0 => XLXI_3_XLXN_21,
      I1 => XLXI_3_XLXN_147,
      I2 => XLXI_3_XLXN_148,
      I3 => XLXI_3_XLXN_150,
      I4 => XLXI_3_XLXN_154,
      O => XLXI_3_XLXN_227
    );
  XLXI_3_XLXI_90 : AND4
    port map (
      I0 => XLXI_3_XLXN_148,
      I1 => XLXI_3_XLXN_24,
      I2 => XLXI_3_XLXN_23,
      I3 => XLXI_3_XLXN_21,
      O => XLXI_3_XLXN_223
    );
  XLXI_3_XLXI_63 : NOR5
    port map (
      I0 => XLXI_3_XLXN_154,
      I1 => XLXI_3_XLXN_152,
      I2 => XLXI_3_XLXN_151,
      I3 => XLXI_3_XLXN_150,