sjall_map.vhd

很好用的7180的驱动

  signal XLXI_2_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_reg_LOGIC_ZERO_156 : STD_LOGIC; 
  signal XLXI_2_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_reg_GROM : STD_LOGIC; 
  signal XLXI_2_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_1_FFY_RST : STD_LOGIC; 
  signal XLXI_2_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_3_FFY_RST : STD_LOGIC; 
  signal XLXI_2_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_5_FFY_RST : STD_LOGIC; 
  signal XLXI_2_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_7_FFY_RST : STD_LOGIC; 
  signal XLXI_3_XLXI_2_1_0_pack_1 : STD_LOGIC; 
  signal XLXI_3_XLXN_453 : STD_LOGIC; 
  signal XLXI_3_XLXN_466_pack_1 : STD_LOGIC; 
  signal XLXI_3_XLXN_578 : STD_LOGIC; 
  signal cblank_OUTMUX_157 : STD_LOGIC; 
  signal din_64_0_IBUF_158 : STD_LOGIC; 
  signal din_64_1_IBUF_159 : STD_LOGIC; 
  signal XLXI_3_XLXI_63_1_0_pack_1 : STD_LOGIC; 
  signal vref_OBUF_160 : STD_LOGIC; 
  signal din_64_2_IBUF_161 : STD_LOGIC; 
  signal din_64_3_IBUF_162 : STD_LOGIC; 
  signal din_64_4_IBUF_163 : STD_LOGIC; 
  signal din_64_5_IBUF_164 : STD_LOGIC; 
  signal XLXI_3_XLXN_581_pack_1 : STD_LOGIC; 
  signal XLXI_3_XLXI_112_AD : STD_LOGIC; 
  signal hsync_OUTMUX_165 : STD_LOGIC; 
  signal XLXI_3_XLXN_452_pack_1 : STD_LOGIC; 
  signal XLXI_3_XLXI_113_AD : STD_LOGIC; 
  signal din_64_6_IBUF_166 : STD_LOGIC; 
  signal din_64_7_IBUF_167 : STD_LOGIC; 
  signal XLXI_3_XLXN_260 : STD_LOGIC; 
  signal din_64_8_IBUF_168 : STD_LOGIC; 
  signal din_64_9_IBUF_169 : STD_LOGIC; 
  signal XLXI_3_CLK_BYMUXNOT : STD_LOGIC; 
  signal wr_en_IBUF_170 : STD_LOGIC; 
  signal XLXI_3_XLXN_478_LOGIC_ONE_171 : STD_LOGIC; 
  signal XLXN_94_OUTMUX_172 : STD_LOGIC; 
  signal XLXN_91 : STD_LOGIC; 
  signal XLXI_3_XLXN_252_pack_1 : STD_LOGIC; 
  signal XLXI_3_XLXN_265 : STD_LOGIC; 
  signal XLXI_2_BU2_U0_gen_as_fgas_DEBUG_RAM_WR_EN : STD_LOGIC; 
  signal din_64_16_IBUF_173 : STD_LOGIC; 
  signal din_64_24_IBUF_174 : STD_LOGIC; 
  signal XLXI_3_XLXN_470_pack_1 : STD_LOGIC; 
  signal XLXI_3_XLXN_595 : STD_LOGIC; 
  signal din_64_32_IBUF_175 : STD_LOGIC; 
  signal din_64_40_IBUF_176 : STD_LOGIC; 
  signal href_OUTMUX_177 : STD_LOGIC; 
  signal vsync_OUTMUX_178 : STD_LOGIC; 
  signal XLXI_3_XLXN_600_LOGIC_ONE_179 : STD_LOGIC; 
  signal XLXI_3_XLXN_600_FFY_RST : STD_LOGIC; 
  signal vref_OUTMUX_180 : STD_LOGIC; 
  signal din_64_10_IBUF_181 : STD_LOGIC; 
  signal XLXI_2_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_4_FFY_RST : STD_LOGIC; 
  signal din_64_11_IBUF_182 : STD_LOGIC; 
  signal din_64_12_IBUF_183 : STD_LOGIC; 
  signal XLXI_2_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_6_FFY_RST : STD_LOGIC; 
  signal din_64_20_IBUF_184 : STD_LOGIC; 
  signal din_64_13_IBUF_185 : STD_LOGIC; 
  signal XLXI_2_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_8_FFY_RST : STD_LOGIC; 
  signal din_64_21_IBUF_186 : STD_LOGIC; 
  signal din_64_14_IBUF_187 : STD_LOGIC; 
  signal XLXI_2_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_10_FFY_RST : STD_LOGIC; 
  signal din_64_22_IBUF_188 : STD_LOGIC; 
  signal XLXI_3_XLXN_40_BYMUXNOT : STD_LOGIC; 
  signal XLXI_3_XLXN_40_FFY_RST : STD_LOGIC; 
  signal din_64_30_IBUF_189 : STD_LOGIC; 
  signal din_64_15_IBUF_190 : STD_LOGIC; 
  signal din_64_23_IBUF_191 : STD_LOGIC; 
  signal din_64_31_IBUF_192 : STD_LOGIC; 
  signal XLXI_2_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_0_FFY_RST : STD_LOGIC; 
  signal XLXI_2_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_2_FFY_RST : STD_LOGIC; 
  signal XLXI_2_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_4_FFY_RST : STD_LOGIC; 
  signal XLXI_2_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_6_FFY_RST : STD_LOGIC; 
  signal XLXI_2_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_0_FFY_RST : STD_LOGIC; 
  signal XLXI_2_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_2_FFY_RST : STD_LOGIC; 
  signal XLXI_2_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_4_FFY_RST : STD_LOGIC; 
  signal XLXI_2_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_6_FFY_RST : STD_LOGIC; 
  signal XLXI_2_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_0_FFY_SET : STD_LOGIC; 
  signal XLXI_2_full_FFY_SET : STD_LOGIC; 
  signal XLXI_2_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_1_FFY_RST : STD_LOGIC; 
  signal XLXI_2_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_3_FFY_RST : STD_LOGIC; 
  signal XLXI_2_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_5_FFY_RST : STD_LOGIC; 
  signal XLXI_2_BU2_U0_gen_as_fgas_debug_wr_pntr_r_2_FFY_RST : STD_LOGIC; 
  signal XLXI_2_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_4_FFY_RST : STD_LOGIC; 
  signal XLXI_2_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_6_FFY_RST : STD_LOGIC; 
  signal XLXI_2_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_8_FFY_RST : STD_LOGIC; 
  signal XLXI_2_empty_FFY_SET : STD_LOGIC; 
  signal XLXI_2_BU2_U0_gen_as_fgas_normgen_inblk_wr_rst_fb_FFY_SET : STD_LOGIC; 
  signal XLXI_2_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_reg_FFY_SET : STD_LOGIC; 
  signal XLXI_2_BU2_U0_gen_as_fgas_normgen_inblk_wr_rst_reg_FFY_SET : STD_LOGIC; 
  signal XLXI_2_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_fb_FFY_SET : STD_LOGIC; 
  signal XLXI_2_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_2_FFY_RST : STD_LOGIC; 
  signal XLXI_2_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_4_FFY_RST : STD_LOGIC; 
  signal XLXI_2_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_6_FFY_RST : STD_LOGIC; 
  signal XLXI_2_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_0_FFY_RST : STD_LOGIC; 
  signal XLXI_2_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_2_FFY_RST : STD_LOGIC; 
  signal XLXI_2_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_4_FFY_RST : STD_LOGIC; 
  signal XLXI_2_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_6_FFY_RST : STD_LOGIC; 
  signal XLXI_2_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_8_FFY_RST : STD_LOGIC; 
  signal XLXI_2_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_0_FFY_RST : STD_LOGIC; 
  signal XLXI_2_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_2_FFY_RST : STD_LOGIC; 
  signal XLXI_2_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_4_FFY_RST : STD_LOGIC; 
  signal XLXI_2_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_6_FFY_RST : STD_LOGIC; 
  signal XLXI_2_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_8_FFY_RST : STD_LOGIC; 
  signal XLXI_2_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r_0_FFX_SET : STD_LOGIC; 
  signal XLXI_2_BU2_U0_gen_as_fgas_debug_rd_pntr_w_6_FFX_RST : STD_LOGIC; 
  signal XLXI_2_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w_0_FFX_RST : STD_LOGIC; 
  signal XLXI_2_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR_0_FFX_RST : STD_LOGIC; 
  signal XLXI_2_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR_0_FFX_RST : STD_LOGIC; 
  signal XLXI_2_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w_0_FFX_SET : STD_LOGIC; 
  signal XLXI_2_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_10_FFX_RST : STD_LOGIC; 
  signal XLXI_2_BU2_U0_gen_as_fgas_debug_rd_pntr_w_8_FFX_RST : STD_LOGIC; 
  signal XLXI_2_BU2_U0_gen_as_fgas_debug_rd_pntr_w_10_FFX_RST : STD_LOGIC; 
  signal XLXI_2_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_1_FFX_RST : STD_LOGIC; 
  signal XLXI_2_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_3_FFX_RST : STD_LOGIC; 
  signal XLXI_2_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_5_FFX_RST : STD_LOGIC; 
  signal XLXI_2_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_7_FFX_RST : STD_LOGIC; 
  signal XLXI_2_BU2_U0_gen_as_fgas_debug_wr_pntr_r_2_FFX_RST : STD_LOGIC; 
  signal XLXI_2_BU2_U0_gen_as_fgas_debug_wr_pntr_r_4_FFX_RST : STD_LOGIC; 
  signal XLXI_2_BU2_U0_gen_as_fgas_debug_wr_pntr_r_7_FFX_RST : STD_LOGIC; 
  signal XLXI_2_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_4_FFX_RST : STD_LOGIC; 
  signal XLXI_2_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_6_FFX_RST : STD_LOGIC; 
  signal XLXI_2_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_8_FFX_RST : STD_LOGIC; 
  signal XLXI_2_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_10_FFX_RST : STD_LOGIC; 
  signal XLXI_2_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_1_FFX_RST : STD_LOGIC; 
  signal XLXI_2_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_3_FFX_RST : STD_LOGIC; 
  signal XLXI_2_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_5_FFX_RST : STD_LOGIC; 
  signal XLXI_2_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x_7_FFX_RST : STD_LOGIC; 
  signal XLXI_2_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_4_FFX_RST : STD_LOGIC; 
  signal XLXI_2_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_6_FFX_RST : STD_LOGIC; 
  signal XLXI_2_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_8_FFX_RST : STD_LOGIC; 
  signal XLXI_2_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x_10_FFX_RST : STD_LOGIC; 
  signal XLXI_2_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_1_FFX_RST : STD_LOGIC; 
  signal XLXI_2_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_3_FFX_RST : STD_LOGIC; 
  signal XLXI_2_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_5_FFX_RST : STD_LOGIC; 
  signal XLXI_2_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2_7_FFX_RST : STD_LOGIC; 
  signal XLXI_2_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_4_FFX_RST : STD_LOGIC; 
  signal XLXI_2_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_6_FFX_RST : STD_LOGIC; 
  signal XLXI_2_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2_8_FFX_RST : STD_LOGIC; 
  signal GND : STD_LOGIC; 
  signal VCC : STD_LOGIC; 
  signal XLXI_2_BU2_U0_gen_as_fgas_DEBUG_RD_PNTR : STD_LOGIC_VECTOR ( 10 downto 0 ); 
  signal XLXI_2_BU2_U0_gen_as_fgas_DEBUG_WR_PNTR : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal XLXI_2_BU2_U0_gen_as_fgas_debug_rd_pntr_plus1_r : STD_LOGIC_VECTOR ( 10 downto 0 ); 
  signal XLXI_2_BU2_U0_gen_as_fgas_debug_wr_pntr_r : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal XLXI_2_BU2_U0_gen_as_fgas_debug_wr_pntr_plus1_w : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal XLXI_2_BU2_U0_gen_as_fgas_debug_wr_pntr_plus2_w : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal XLXI_2_BU2_U0_gen_as_fgas_debug_rd_pntr_w : STD_LOGIC_VECTOR ( 10 downto 3 ); 
  signal XLXI_2_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x2 : STD_LOGIC_VECTOR ( 10 downto 3 ); 
  signal XLXI_2_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal XLXI_2_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x2 : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal XLXI_2_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc : STD_LOGIC_VECTOR ( 10 downto 3 ); 
  signal XLXI_2_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_pntr_gc_x : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal XLXI_2_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_pntr_gc_x : STD_LOGIC_VECTOR ( 10 downto 3 ); 
  signal XLXI_2_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c2_v1 : STD_LOGIC_VECTOR ( 5 downto 0 ); 
  signal XLXI_2_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_c1_v1 : STD_LOGIC_VECTOR ( 5 downto 0 ); 
  signal XLXI_2_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Result : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal XLXI_2_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Result : STD_LOGIC_VECTOR ( 10 downto 0 ); 
  signal XLXI_2_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_rd_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Result : STD_LOGIC_VECTOR ( 10 downto 0 ); 
  signal XLXI_2_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus1_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Result : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal XLXI_2_BU2_U0_gen_as_fgas_normgen_cntblk_gen_cntr_gen_wr_cntr_plus2_gen_bin_cnt_top_bin_cnt_top_gen_bsc_bin_cnt_bld_bin_cnt_Result : STD_LOGIC_VECTOR ( 7 downto 0 ); 
begin
  XLXN_94 <= NlwRenamedSig_OI_XLXN_94;
  XLXI_3_XLXN_48_BYMUX : X_INV
    port map (
      I => XLXI_3_XLXN_48,
      O => XLXI_3_XLXN_48_BYMUXNOT
    );
  XLXI_3_XLXI_3_I_Q0_I_36_35 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => XLXI_3_XLXN_48_BYMUXNOT,
      CE => XLXI_3_XLXN_4_0,
      CLK => XLXI_3_CLK,
      SET => GND,
      RST => XLXI_3_XLXN_48_FFY_RST,
      O => XLXI_3_XLXN_48
    );
  XLXI_3_XLXN_48_FFY_RSTOR : X_BUF
    port map (
      I => XLXI_3_XLXN_260_0,
      O => XLXI_3_XLXN_48_FFY_RST
    );
  din_64_17_IMUX : X_BUF
    port map (
      I => din_64_17_IBUF_11,
      O => din_64_17_IBUF_0
    );
  din_64_17_IBUF : X_BUF
    port map (
      I => din_64(17),
      O => din_64_17_IBUF_11
    );
  din_64_25_IMUX : X_BUF
    port map (
      I => din_64_25_IBUF_12,
      O => din_64_25_IBUF_0
    );
  din_64_25_IBUF : X_BUF
    port map (
      I => din_64(25),
      O => din_64_25_IBUF_12
    );
  din_64_33_IMUX : X_BUF
    port map (
      I => din_64_33_IBUF_13,
      O => din_64_33_IBUF_0
    );
  din_64_33_IBUF : X_BUF
    port map (
      I => din_64(33),
      O => din_64_33_IBUF_13
    );
  din_64_41_IMUX : X_BUF
    port map (
      I => din_64_41_IBUF_14,
      O => din_64_41_IBUF_0
    );
  din_64_41_IBUF : X_BUF
    port map (
      I => din_64(41),
      O => din_64_41_IBUF_14
    );
  din_64_18_IMUX : X_BUF
    port map (
      I => din_64_18_IBUF_15,
      O => din_64_18_IBUF_0