sjall_map.vhd

很好用的7180的驱动

--------------------------------------------------------------------------------
-- Copyright (c) 1995-2007 Xilinx, Inc.  All rights reserved.
--------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor: Xilinx
-- \   \   \/     Version: J.30
--  \   \         Application: netgen
--  /   /         Filename: sjall_map.vhd
-- /___/   /\     Timestamp: Tue Jul 08 20:40:13 2008
-- \   \  /  \ 
--  \___\/\___\
--             
-- Command	: -intstyle ise -s 7 -pcf sjall.pcf -rpw 100 -tpw 0 -ar Structure -tm sjall -w -dir netgen/map -ofmt vhdl -sim sjall_map.ncd sjall_map.vhd 
-- Device	: 2s50etq144-7 (PRODUCTION 1.18 2006-10-19)
-- Input file	: sjall_map.ncd
-- Output file	: E:\Application\SJ\FPGA\netgen\map\sjall_map.vhd
-- # of Entities	: 1
-- Design Name	: sjall
-- Xilinx	: C:\Xilinx91i
--             
-- Purpose:    
--     This VHDL netlist is a verification model and uses simulation 
--     primitives which may not represent the true implementation of the 
--     device, however the netlist is functionally correct and should not 
--     be modified. This file cannot be synthesized and should only be used 
--     with supported simulation tools.
--             
-- Reference:  
--     Development System Reference Guide, Chapter 23
--     Synthesis and Simulation Design Guide, Chapter 6
--             
--------------------------------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library SIMPRIM;
use SIMPRIM.VCOMPONENTS.ALL;
use SIMPRIM.VPACKAGE.ALL;

entity sjall is
  port (
    vsync : out STD_LOGIC; 
    wr_en : in STD_LOGIC := 'X'; 
    href : out STD_LOGIC; 
    clk_40 : in STD_LOGIC := 'X'; 
    vref : out STD_LOGIC; 
    clk_27M : in STD_LOGIC := 'X'; 
    cblank : out STD_LOGIC; 
    wr_133 : in STD_LOGIC := 'X'; 
    hsync : out STD_LOGIC; 
    rd_27clk : in STD_LOGIC := 'X'; 
    XLXN_94 : out STD_LOGIC; 
    dout_8 : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
    din_64 : in STD_LOGIC_VECTOR ( 63 downto 0 ) 
  );
end sjall;

architecture Structure of sjall is
  signal NlwRenamedSig_OI_XLXN_94 : STD_LOGIC; 
  signal XLXI_3_XLXN_48 : STD_LOGIC; 
  signal XLXI_3_XLXN_4_0 : STD_LOGIC; 
  signal XLXI_3_CLK : STD_LOGIC; 
  signal XLXI_3_XLXN_260_0 : STD_LOGIC; 
  signal din_64_17_IBUF_0 : STD_LOGIC; 
  signal din_64_25_IBUF_0 : STD_LOGIC; 
  signal din_64_33_IBUF_0 : STD_LOGIC; 
  signal din_64_41_IBUF_0 : STD_LOGIC; 
  signal din_64_18_IBUF_0 : STD_LOGIC; 
  signal din_64_26_IBUF_0 : STD_LOGIC; 
  signal din_64_34_IBUF_0 : STD_LOGIC; 
  signal din_64_42_IBUF_0 : STD_LOGIC; 
  signal din_64_50_IBUF_0 : STD_LOGIC; 
  signal din_64_19_IBUF_0 : STD_LOGIC; 
  signal din_64_27_IBUF_0 : STD_LOGIC; 
  signal din_64_35_IBUF_0 : STD_LOGIC; 
  signal din_64_43_IBUF_0 : STD_LOGIC; 
  signal din_64_51_IBUF_0 : STD_LOGIC; 
  signal din_64_28_IBUF_0 : STD_LOGIC; 
  signal din_64_36_IBUF_0 : STD_LOGIC; 
  signal din_64_44_IBUF_0 : STD_LOGIC; 
  signal din_64_52_IBUF_0 : STD_LOGIC; 
  signal din_64_60_IBUF_0 : STD_LOGIC; 
  signal din_64_29_IBUF_0 : STD_LOGIC; 
  signal din_64_37_IBUF_0 : STD_LOGIC; 
  signal din_64_45_IBUF_0 : STD_LOGIC; 
  signal din_64_53_IBUF_0 : STD_LOGIC; 
  signal din_64_61_IBUF_0 : STD_LOGIC; 
  signal din_64_38_IBUF_0 : STD_LOGIC; 
  signal din_64_46_IBUF_0 : STD_LOGIC; 
  signal din_64_54_IBUF_0 : STD_LOGIC; 
  signal din_64_62_IBUF_0 : STD_LOGIC; 
  signal din_64_39_IBUF_0 : STD_LOGIC; 
  signal din_64_47_IBUF_0 : STD_LOGIC; 
  signal din_64_55_IBUF_0 : STD_LOGIC; 
  signal din_64_63_IBUF_0 : STD_LOGIC; 
  signal din_64_48_IBUF_0 : STD_LOGIC; 
  signal din_64_56_IBUF_0 : STD_LOGIC; 
  signal din_64_49_IBUF_0 : STD_LOGIC; 
  signal din_64_57_IBUF_0 : STD_LOGIC; 
  signal din_64_58_IBUF_0 : STD_LOGIC; 
  signal din_64_59_IBUF_0 : STD_LOGIC; 
  signal dout_8_0_OBUF_0 : STD_LOGIC; 
  signal dout_8_1_OBUF_1 : STD_LOGIC; 
  signal dout_8_2_OBUF_2 : STD_LOGIC; 
  signal dout_8_3_OBUF_3 : STD_LOGIC; 
  signal dout_8_4_OBUF_4 : STD_LOGIC; 
  signal dout_8_5_OBUF_5 : STD_LOGIC; 
  signal dout_8_6_OBUF_6 : STD_LOGIC; 
  signal dout_8_7_OBUF_7 : STD_LOGIC; 
  signal clk_40_BUFGP : STD_LOGIC; 
  signal XLXI_7_XLXN_76 : STD_LOGIC; 
  signal XLXI_7_XLXN_77 : STD_LOGIC; 
  signal XLXI_7_XLXN_75 : STD_LOGIC; 
  signal XLXI_7_XLXN_97 : STD_LOGIC; 
  signal wr_133_BUFGP : STD_LOGIC; 
  signal rd_27clk_BUFGP : STD_LOGIC; 
  signal XLXI_2_BU2_U0_gen_as_fgas_normgen_memblk_tmp_ram_rd_en_0 : STD_LOGIC; 
  signal XLXI_2_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_fb : STD_LOGIC; 
  signal XLXI_2_BU2_U0_gen_as_fgas_normgen_inblk_wr_rst_fb_8 : STD_LOGIC; 
  signal XLXI_2_BU2_U0_gen_as_fgas_DEBUG_RAM_WR_EN_0 : STD_LOGIC; 
  signal GLOBAL_LOGIC0 : STD_LOGIC; 
  signal din_64_30_IBUF_0 : STD_LOGIC; 
  signal din_64_31_IBUF_0 : STD_LOGIC; 
  signal din_64_22_IBUF_0 : STD_LOGIC; 
  signal din_64_23_IBUF_0 : STD_LOGIC; 
  signal din_64_14_IBUF_0 : STD_LOGIC; 
  signal din_64_15_IBUF_0 : STD_LOGIC; 
  signal din_64_6_IBUF_0 : STD_LOGIC; 
  signal din_64_7_IBUF_0 : STD_LOGIC; 
  signal din_64_10_IBUF_0 : STD_LOGIC; 
  signal din_64_11_IBUF_0 : STD_LOGIC; 
  signal din_64_2_IBUF_0 : STD_LOGIC; 
  signal din_64_3_IBUF_0 : STD_LOGIC; 
  signal din_64_20_IBUF_0 : STD_LOGIC; 
  signal din_64_21_IBUF_0 : STD_LOGIC; 
  signal din_64_12_IBUF_0 : STD_LOGIC; 
  signal din_64_13_IBUF_0 : STD_LOGIC; 
  signal din_64_4_IBUF_0 : STD_LOGIC; 
  signal din_64_5_IBUF_0 : STD_LOGIC; 
  signal din_64_40_IBUF_0 : STD_LOGIC; 
  signal din_64_32_IBUF_0 : STD_LOGIC; 
  signal din_64_24_IBUF_0 : STD_LOGIC; 
  signal din_64_16_IBUF_0 : STD_LOGIC; 
  signal din_64_8_IBUF_0 : STD_LOGIC; 
  signal din_64_9_IBUF_0 : STD_LOGIC; 
  signal din_64_0_IBUF_0 : STD_LOGIC; 
  signal din_64_1_IBUF_0 : STD_LOGIC; 
  signal XLXI_2_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_comp2out : STD_LOGIC; 
  signal XLXI_2_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_elogic_comp1out : STD_LOGIC; 
  signal GLOBAL_LOGIC1 : STD_LOGIC; 
  signal XLXI_2_BU2_U0_gen_as_fgas_DEBUG_RAM_RD_EN_0 : STD_LOGIC; 
  signal XLXI_2_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_FULL_NONREG_i_map92_0 : STD_LOGIC; 
  signal XLXI_2_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_FULL_NONREG_i_map81_0 : STD_LOGIC; 
  signal XLXI_2_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_FULL_NONREG_i_map69_0 : STD_LOGIC; 
  signal XLXI_2_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_FULL_NONREG_i_map58_0 : STD_LOGIC; 
  signal XLXI_2_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_FULL_NONREG_i353_SW0_O : STD_LOGIC; 
  signal XLXI_2_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_FULL_NONREG_i_map23_0 : STD_LOGIC; 
  signal XLXI_2_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_FULL_NONREG_i_map45_0 : STD_LOGIC; 
  signal XLXI_2_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_FULL_NONREG_i_map34_0 : STD_LOGIC; 
  signal XLXI_2_full : STD_LOGIC; 
  signal XLXI_2_BU2_U0_gen_as_fgas_normgen_flblk_thrmod_flogic_FULL_NONREG_i72_O : STD_LOGIC; 
  signal XLXI_2_BU2_U0_gen_as_fgas_N301_0 : STD_LOGIC; 
  signal XLXI_3_XLXN_6_0 : STD_LOGIC; 
  signal XLXI_3_XLXN_148 : STD_LOGIC; 
  signal XLXI_3_XLXN_147 : STD_LOGIC; 
  signal XLXI_3_XLXN_151 : STD_LOGIC; 
  signal XLXI_3_XLXN_150 : STD_LOGIC; 
  signal XLXI_3_XLXN_265_0 : STD_LOGIC; 
  signal XLXI_3_XLXN_8_0 : STD_LOGIC; 
  signal XLXI_3_XLXN_478 : STD_LOGIC; 
  signal XLXI_3_XLXN_10 : STD_LOGIC; 
  signal XLXI_3_XLXN_51 : STD_LOGIC; 
  signal XLXI_3_XLXN_12 : STD_LOGIC; 
  signal XLXI_3_XLXN_11 : STD_LOGIC; 
  signal XLXI_2_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_PNTR_B_xor0003 : STD_LOGIC; 
  signal XLXI_2_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_rdx_PNTR_B_xor0001 : STD_LOGIC; 
  signal XLXI_3_XLXN_49 : STD_LOGIC; 
  signal XLXI_3_XLXN_40 : STD_LOGIC; 
  signal XLXI_3_XLXN_39 : STD_LOGIC; 
  signal XLXI_3_XLXN_140_0 : STD_LOGIC; 
  signal XLXI_3_XLXN_146_0 : STD_LOGIC; 
  signal XLXI_3_XLXN_22 : STD_LOGIC; 
  signal XLXI_3_XLXN_21 : STD_LOGIC; 
  signal XLXI_3_XLXN_24 : STD_LOGIC; 
  signal XLXI_3_XLXN_23 : STD_LOGIC; 
  signal XLXI_3_XLXN_38 : STD_LOGIC; 
  signal XLXI_3_XLXN_2_0 : STD_LOGIC; 
  signal XLXI_2_BU2_U0_gen_as_fgas_normgen_flblk_clkmod_cx_wrx_PNTR_B_xor0002 : STD_LOGIC; 
  signal XLXI_3_XLXI_92_1_0_0 : STD_LOGIC; 
  signal XLXI_3_XLXI_2_1_0 : STD_LOGIC; 
  signal XLXI_3_XLXI_4_1_0 : STD_LOGIC; 
  signal XLXI_2_empty : STD_LOGIC; 
  signal XLXI_3_XLXN_241 : STD_LOGIC; 
  signal XLXI_3_XLXN_154 : STD_LOGIC; 
  signal XLXI_3_XLXN_152 : STD_LOGIC; 
  signal XLXI_3_XLXI_104_1_0_0 : STD_LOGIC; 
  signal XLXI_3_XLXN_223_0 : STD_LOGIC; 
  signal XLXI_3_XLXI_62_1_0_0 : STD_LOGIC; 
  signal XLXI_3_XLXI_96_1_0_0 : STD_LOGIC; 
  signal XLXI_3_XLXN_137 : STD_LOGIC; 
  signal XLXI_3_XLXN_242 : STD_LOGIC; 
  signal XLXI_2_BU2_U0_gen_as_fgas_normgen_inblk_wr_rst_reg_9 : STD_LOGIC; 
  signal XLXI_3_XLXI_103_1_0 : STD_LOGIC; 
  signal XLXI_3_XLXN_221_0 : STD_LOGIC; 
  signal wr_en_IBUF_0 : STD_LOGIC; 
  signal XLXI_2_BU2_U0_gen_as_fgas_normgen_inblk_rd_rst_reg_10 : STD_LOGIC; 
  signal XLXI_3_XLXN_453_0 : STD_LOGIC; 
  signal XLXI_3_XLXN_139_0 : STD_LOGIC; 
  signal XLXI_3_XLXN_142_0 : STD_LOGIC; 
  signal XLXI_3_XLXN_141 : STD_LOGIC; 
  signal XLXI_2_BU2_U0_gen_as_fgas_N32 : STD_LOGIC; 
  signal XLXI_3_XLXI_94_I35 : STD_LOGIC; 
  signal XLXI_3_XLXN_224_0 : STD_LOGIC; 
  signal XLXI_3_XLXI_57_I35 : STD_LOGIC; 
  signal XLXI_3_XLXI_225_S1_0 : STD_LOGIC; 
  signal XLXI_3_XLXI_225_S0_0 : STD_LOGIC; 
  signal XLXI_3_XLXI_56_I35 : STD_LOGIC; 
  signal XLXI_3_XLXI_224_S1_0 : STD_LOGIC; 
  signal XLXI_3_XLXI_224_S0_0 : STD_LOGIC; 
  signal XLXI_3_XLXN_466 : STD_LOGIC; 
  signal XLXI_3_XLXN_578_0 : STD_LOGIC; 
  signal XLXI_3_XLXI_63_1_0 : STD_LOGIC; 
  signal vref_OBUF_0 : STD_LOGIC; 
  signal XLXI_3_XLXN_581 : STD_LOGIC; 
  signal XLXI_3_XLXN_452 : STD_LOGIC;