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📄 aduc702x.lst

📁 arm的DA程序源码
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                        239             
                        240     
                        241     
                        242                                                                             
00080000                243     AREA   STARTUPCODE, CODE, AT 0x00080000
                        244            PUBLIC  __startup
                        245     
                        246            EXTERN  CODE32 (?C?INIT)
                        247     
                        248     __startup       PROC    CODE32
                        249     
                        250     
                        251     
                        252     EXTERN CODE32 (Undef_Handler?A)
                        253     EXTERN CODE32 (SWI_Handler?A)
                        254     EXTERN CODE32 (PAbt_Handler?A)
                        255     EXTERN CODE32 (DAbt_Handler?A)
                        256     EXTERN CODE32 (IRQ_Handler?A)
AA MACRO ASSEMBLER RADUC702X                                                                18/11/07 00:38:34 PAGE     5

                        257     EXTERN CODE32 (FIQ_Handler?A)
                        258     
                        259     
                        260     
                        261     
                        262     
00080000 E59FF000       263     Vectors:        LDR     PC,Reset_Addr         
00080004 E59FF000       264                     LDR     PC,Undef_Addr
00080008 E59FF000       265                     LDR     PC,SWI_Addr
0008000C E59FF000       266                     LDR     PC,PAbt_Addr
00080010 E59FF000       267                     LDR     PC,DAbt_Addr
00080014 E1A00000       268                     NOP                             
00080018 E59FF000       269                     LDR     PC,IRQ_Addr
0008001C E59FF000       270                     LDR     PC,FIQ_Addr
                        271     
00080020 00080040 R     272     Reset_Addr:     DD      Reset_Handler
00080024 00000000 E     273     Undef_Addr:     DD      Undef_Handler?A
00080028 00000000 E     274     SWI_Addr:       DD      SWI_Handler?A
0008002C 00000000 E     275     PAbt_Addr:      DD      PAbt_Handler?A
00080030 00000000 E     276     DAbt_Addr:      DD      DAbt_Handler?A
00080034 00000000       277                     DD      0                       
00080038 00000000 E     278     IRQ_Addr:       DD      IRQ_Handler?A
0008003C 00000000 E     279     FIQ_Addr:       DD      FIQ_Handler?A
                        280     
                        281     
                        282     
                        283     
00080040                284     Reset_Handler:  
                        285     
                        286     
                        287     
                        288     IF (PLL_SETUP != 0)
00080040 E59F0034       289                     LDR     R0, =MMR_BASE
00080044 E3A01001       290                     MOV     R1, #0x01         
00080048 E5801404       291                     STR     R1, [R0,#POWKEY1_OFFSET]          
0008004C E3A01001       292                     MOV     R1, #PLLCFG_Val      
00080050 E5801408       293                     STR     R1, [R0,#POWCON_OFFSET]    
00080054 E3A010F4       294                     MOV     R1, #0xF4
00080058 E580140C       295                     STR     R1, [R0,#POWKEY2_OFFSET]
                        296     ENDIF   ; PLL_SETUP
                        297     
                        298     
                        299     
                        300     IF (GPIO_SETUP != 0)
                                
                                                ADR     R10, GPIO_CFG           
                                                LDMIA   R10, {R0-R5}            
                                                STMIA   R0, {R1-R5}             
                                                B       GPIO_END
                                
                                GPIO_CFG:       DD      GPIOBASE
                                                DD      GP0CON_Val
                                                DD      GP1CON_Val
                                                DD      GP2CON_Val
                                                DD      GP3CON_Val
                                                DD      GP4CON_Val
                                GPIO_END:
                                
                                ENDIF   ; GPIO_SETUP
                        316     
                        317     
                        318     
                        319     IF (XM_SETUP != 0)
                                
                                                ADR     R10, XM_CFG             
                                                LDMIA   R10, {R0-R9}            
AA MACRO ASSEMBLER RADUC702X                                                                18/11/07 00:38:34 PAGE     6

                                                STR     R1, [R0],#0x10          
                                                STMIA   R0, {R2-R9}             
                                                B       XM_END
                                
                                XM_CFG:         DD      XMBASE
                                                DD      XMCFG_Val
                                                DD      XM0CON_Val
                                                DD      XM1CON_Val
                                                DD      XM2CON_Val
                                                DD      XM3CON_Val
                                                DD      XM0PAR_Val
                                                DD      XM1PAR_Val
                                                DD      XM2PAR_Val
                                                DD      XM3PAR_Val
                                XM_END:
                                
                                ENDIF   ; XM_SETUP
                        340     
                        341     
                        342     
                        343     
                        344     
                        345     $if  (RAM_INTVEC)
                                                ADR     R8, Vectors         ; Source
                                                LDR     R9, =0x00010000     ; Destination
                                                LDMIA   R8!, {R0-R7}        ; Load Vectors 
                                                STMIA   R9!, {R0-R7}        ; Store Vectors 
                                                LDMIA   R8!, {R0-R7}        ; Load Handler Addresses 
                                                STMIA   R9!, {R0-R7}        ; Store Handler Addresses 
                                                LDR     R0, =MMR_BASE
                                                MOV     R1, #1     
                                                STR     R1, [R0,#REMAP_OFFSET]          
                                $endif 
                        356     
                        357     
                        358     
0008005C E59F0034       359                     LDR     R0, =Top_Stack
                        360     
                        361     
00080060 E321F0DB       362                     MSR     CPSR_c, #Mode_UND|I_Bit|F_Bit
00080064 E1A0D000       363                     MOV     SP, R0
00080068 E2400004       364                     SUB     R0, R0, #UND_Stack_Size
                        365     
                        366     
0008006C E321F0D7       367                     MSR     CPSR_c, #Mode_ABT|I_Bit|F_Bit
00080070 E1A0D000       368                     MOV     SP, R0
00080074 E2400004       369                     SUB     R0, R0, #ABT_Stack_Size
                        370     
                        371     
00080078 E321F0D1       372                     MSR     CPSR_c, #Mode_FIQ|I_Bit|F_Bit
0008007C E1A0D000       373                     MOV     SP, R0
00080080 E2400004       374                     SUB     R0, R0, #FIQ_Stack_Size
                        375     
                        376     
00080084 E321F0D2       377                     MSR     CPSR_c, #Mode_IRQ|I_Bit|F_Bit
00080088 E1A0D000       378                     MOV     SP, R0
0008008C E2400080       379                     SUB     R0, R0, #IRQ_Stack_Size
                        380     
                        381     
00080090 E321F0D3       382                     MSR     CPSR_c, #Mode_SVC|I_Bit|F_Bit
00080094 E1A0D000       383                     MOV     SP, R0
00080098 E2400004       384                     SUB     R0, R0, #SVC_Stack_Size
                        385     
                        386     
0008009C E321F010       387                     MSR     CPSR_c, #Mode_USR
000800A0 E1A0D000       388                     MOV     SP, R0
AA MACRO ASSEMBLER RADUC702X                                                                18/11/07 00:38:34 PAGE     7

                        389     
                        390     
000800A4 E59F0034       391                     LDR     R0,=?C?INIT
000800A8 E3100001       392                     TST     R0,#1       ; Bit-0 set: main is Thumb
000800AC E3AFE034       393                     LDREQ   LR,=exit?A  ; ARM Mode
000800B0 E3AFE034       394                     LDRNE   LR,=exit?T  ; Thumb Mode
000800B4 E12FFF10       395                     BX      R0
                        396                     ENDP
                        397     
                        398     PUBLIC exit?A
                        399     exit?A          PROC    CODE32
000800B8 EAFFFFFE       400                     B       exit?A
                        401                     ENDP
                        402     
                        403     PUBLIC exit?T
                        404     exit?T          PROC    CODE16
000800BC E7FE           405                     B       exit?T
                        406                     ENDP
                        407     
                        408                     END
AA MACRO ASSEMBLER RADUC702X                                                                18/11/07 00:38:34 PAGE     8

SYMBOL TABLE LISTING
------ ----- -------


N A M E             T Y P E  V A L U E     ATTRIBUTES

?C?INIT. . . . . .  C  ADDR  -------       EXT
ABT_Stack_Size . .  -- ----  0004H     A   
DAbt_Addr. . . . .  C  ADDR  080030H   R   SEG=STARTUPCODE
DAbt_Handler?A . .  C  ADDR  -------       EXT
FIQ_Addr . . . . .  C  ADDR  08003CH   R   SEG=STARTUPCODE
FIQ_Handler?A. . .  C  ADDR  -------       EXT
FIQ_Stack_Size . .  -- ----  0004H     A   
F_Bit. . . . . . .  -- ----  0040H     A   
GP0CON_Val . . . .  -- ----  0000H     A   
GP1CON_Val . . . .  -- ----  0000H     A   
GP2CON_Val . . . .  -- ----  0000H     A   
GP3CON_Val . . . .  -- ----  0000H     A   
GP4CON_Val . . . .  -- ----  0000H     A   
GPIOBASE . . . . .  -- ----  FFFFF400H A   
GPIO_SETUP . . . .  -- ----  0000H     A   
IRQ_Addr . . . . .  C  ADDR  080038H   R   SEG=STARTUPCODE
IRQ_Handler?A. . .  C  ADDR  -------       EXT
IRQ_Stack_Size . .  -- ----  0080H     A   
I_Bit. . . . . . .  -- ----  0080H     A   
MMR_BASE . . . . .  -- ----  FFFF0000H A   
Mode_ABT . . . . .  -- ----  0017H     A   
Mode_FIQ . . . . .  -- ----  0011H     A   
Mode_IRQ . . . . .  -- ----  0012H     A   
Mode_SVC . . . . .  -- ----  0013H     A   
Mode_SYS . . . . .  -- ----  001FH     A   
Mode_UND . . . . .  -- ----  001BH     A   
Mode_USR . . . . .  -- ----  0010H     A   
PAbt_Addr. . . . .  C  ADDR  08002CH   R   SEG=STARTUPCODE
PAbt_Handler?A . .  C  ADDR  -------       EXT
PLLCFG_Val . . . .  -- ----  0001H     A   
PLL_SETUP. . . . .  -- ----  0001H     A   
POWCON_OFFSET. . .  -- ----  0408H     A   
POWKEY1_OFFSET . .  -- ----  0404H     A   
POWKEY2_OFFSET . .  -- ----  040CH     A   
REMAP_OFFSET . . .  -- ----  0220H     A   
Reset_Addr . . . .  C  ADDR  080020H   R   SEG=STARTUPCODE
Reset_Handler. . .  C  ADDR  080040H   R   SEG=STARTUPCODE
STACK. . . . . . .  D  SEG   0490H         REL=UNIT, ALN=BYTE
STARTUPCODE. . . .  C  SEG   0800BEH       REL=ABS, ALN=BYTE
SVC_Stack_Size . .  -- ----  0004H     A   
SWI_Addr . . . . .  C  ADDR  080028H   R   SEG=STARTUPCODE
SWI_Handler?A. . .  C  ADDR  -------       EXT
Top_Stack. . . . .  D  ADDR  0490H     R   SEG=STACK
UND_Stack_Size . .  -- ----  0004H     A   
USR_Stack_Size . .  -- ----  0400H     A   
Undef_Addr . . . .  C  ADDR  080024H   R   SEG=STARTUPCODE
Undef_Handler?A. .  C  ADDR  -------       EXT
Vectors. . . . . .  C  ADDR  080000H   R   SEG=STARTUPCODE
XM0CON_Val . . . .  -- ----  0000H     A   
XM0PAR_Val . . . .  -- ----  70FFH     A   
XM1CON_Val . . . .  -- ----  0000H     A   
XM1PAR_Val . . . .  -- ----  70FFH     A   
XM2CON_Val . . . .  -- ----  0000H     A   
XM2PAR_Val . . . .  -- ----  70FFH     A   
XM3CON_Val . . . .  -- ----  0000H     A   
XM3PAR_Val . . . .  -- ----  70FFH     A   
XMBASE . . . . . .  -- ----  FFFFF000H A   
XMCFG_Val. . . . .  -- ----  0001H     A   
XM_SETUP . . . . .  -- ----  0000H     A   
__startup. . . . .  C  ADDR  080000H   R   SEG=STARTUPCODE
AA MACRO ASSEMBLER RADUC702X                                                                18/11/07 00:38:34 PAGE     9

exit?A . . . . . .  C  ADDR  0800B8H   R   SEG=STARTUPCODE
exit?T . . . . . .  C  ADDR  0800BCH   R   SEG=STARTUPCODE

ASSEMBLY COMPLETE.  0 WARNING(S), 0 ERROR(S).

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