📄 8733_spi_mt.dt
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;****************************************************************;
; TILTE: eKTP8733N SPI Transfer DEMO CODE ;
; FUNCTION: eKTP8733N SPI Transfer as Master ;
; COMPANY: ELAN MICROELECTRONICS (SZ) LTD. ;
;****************************************************************;
; 该范例以eKTP8733N作为MASTER,MCU循环重复发送10个不同数据,每发送一
; 个数据的时间间隔约1.6S. 发送的10组数据为: 0FH, F0H, 5AH, A5H, 5FH,
; F5H, AFH, FAH, 55H, AAH; Fs: IRC 4MHz
;-----------------------------------------------------------------
; bank 0
PC == 0x02 ; Program Counter & Stack
STATUS == 0x03 ;
C == 0 ; Carry flag
Z == 2 ; Zero flag
PORT5 == 0x05 ; PORT5 I/O register
PORT6 == 0x06 ; PORT6 I/O register
PORT7 == 0x07 ; PORT7 I/O register
PORT8 == 0x08 ; PORT8 I/O register
B0RE == 0x0E
ISR1 == 0x0E ; Interrupt status register 1
TCIF == 4 ; TCC interrupt flag
B0RF == 0x0F
ISR2 == 0x0F ; Interrupt status register 2
SPIIF == 3 ; SPI interrupt flag
; bank 1
IOC5 == 0x05 ; PORT5 I/O control register
IOC6 == 0x06 ; PORT6 I/O control register
IOC7 == 0x07 ; PORT7 I/O control register
IOC8 == 0x08 ; PORT8 I/O control register
WDTCR == 0x0C ; WDT timer control register
B1RE == 0x0E
IMR1 == 0x0E ; Interrupt mask register 1
B1RF == 0x0F
IMR2 == 0x0F ; Interrupt mask register 2
; bank 2
TCCCR == 0x05 ; Time Clock/Counter control register
; bank 3
TCC == 0x05 ; Time Clock/Counter
COBS1 == 0x06 ; Code option: Type&IRC calibration register
COBS2 == 0x07 ; Code option: LVR, Noise, IRC, RCOUT register
; bank 7
SPIS == 0x0C ; SPI status register
SPICR == 0x0D ; SPI control register
SSE == 4
SPIR == 0x0E ; SPI read buffer
SPIW == 0x0F ; SPI write buffer
;
DATA_BUF == 0x1E ; Data buffer
TEMP == 0x1F
;-----------------------------------------------------------------
ORG 0x00
NOP
JMP Main
ORG 0X1B ; SPI interrupt vector
LJMP SPI_INT ; To SPI interrupt program
ORG 0x50
;-----------------------------------------------------------------
SPI_INT:
; User code
; ...
BANK 0
BC ISR2, SPIIF
RETI
;-----------------------------------------------------------------
Main:
NOP
BANK 0
CLR PORT5 ; PORT5 output logic "0"
CLR PORT6 ; PORT6 output logic "0"
CLR PORT7 ; PORT7 output logic "0"
CLR PORT8 ; PORT8 output logic "0"
CLR 0x1E
CLR 0x1F
BANK 1
CLR IOC5 ; Set port5 as output pin
MOV A, @0x08
MOV IOC6, A ; Set P63 as input pin
CLR IOC7 ; Set port7 as output pin
CLR IOC8 ; Set port8 as output pin
MOV A, @0x00
MOV WDTCR, A ; Disable WDT
MOV A, @0x10
MOV IMR1, A ; Enable TCC interrupt
MOV A, @0x00
MOV IMR2, A ; Disable SPI interrupt
BANK 2
MOV A, @0x00
MOV TCCCR, A ; TCC rate --> 1:1
BANK 3
MOV A, @0x3F ; Select ekt8733, irc: 1*F
MOV COBS1, A
MOV A, @0x30 ; Select IRC 4MHz
MOV COBS2, A
CLR TCC
BANK 7
MOV A, @01000000b ; Shift left, SDO delay time: 16clk,
MOV SPIS, A ; disable open-drain
MOV A, @01001100b ; Data shift out rising edge, is on hold during low
MOV SPICR, A ; Enable SPI mode, after data output sdo remain low
; Selecting SPI Baud Rate is Fosc/32
;-----------------------------------------------
LOOP:
MOV A, DATA_BUF ; To get data to transfer
CALL Data_Tbl
BANK 7
MOV SPIW, A ; Write data to buffer
BS SPICR, SSE ; Start to shift data
JBC SPICR, SSE ; Wait to finish shift data
JMP $-1
CLR TEMP
;JMP LOOP
WAITLP:
BANK 0
JBS ISR1, TCIF ; Wait for about 1.28Ms to shift next data
JMP $-1
CLR ISR1 ; Clear TCC flag
INC TEMP
MOV A, TEMP
ADD A, @256-20 ; 256*1*20/4M
JBS STATUS, C
JMP WAITLP
;
INC DATA_BUF
MOV A, DATA_BUF ; After shifting 10 bytes data, repeat
ADD A, @256-10
JBC STATUS, C
CLR DATA_BUF
JMP LOOP
;-----------------------------------------------
Data_Tbl:
ADD PC, A
RETL 0x0F ; 0
RETL 0xF0 ; 1
RETL 0x5A ; 2
RETL 0xA5 ; 3
RETL 0x5F ; 4
RETL 0xF5 ; 5
RETL 0xAF ; 6
RETL 0xFA ; 7
RETL 0x55 ; 8
RETL 0xAA ; 9
;-----------------------------------------------
END
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