📄 cc1100.lst
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170 // Length configuration = (1) Variable length packets, packet length configured by the first received byte
- after sync word.
171 // Packetlength = 255
172 // Preamble count = (2) 4 bytes
173 // Append status = 1
174 // Address check = (0) No address check
175 // FIFO autoflush = 0
176 // Device address = 0
177 // GDO0 signal selection = ( 6) Asserts when sync word has been sent / received, and de-asserts at the end
C51 COMPILER V8.02 CC1100 11/15/2007 11:37:22 PAGE 4
- of the packet
178 // GDO2 signal selection = (11) Serial Clock
179 const RF_SETTINGS rfSettings = {
180 0x00,
181 0x0B, // FSCTRL1 Frequency synthesizer control.
182 0x00, // FSCTRL0 Frequency synthesizer control.
183 0x10, // FREQ2 Frequency control word, high byte.
184 0xA7, // FREQ1 Frequency control word, middle byte.
185 0x62, // FREQ0 Frequency control word, low byte.
186 0x2D, // MDMCFG4 Modem configuration.
187 0x3B, // MDMCFG3 Modem configuration.
188 0x73, // MDMCFG2 Modem configuration.
189 0x22, // MDMCFG1 Modem configuration.
190 0xF8, // MDMCFG0 Modem configuration.
191
192 0x00, // CHANNR Channel number.
193 0x00, // DEVIATN Modem deviation setting (when FSK modulation is enabled).
194 0xB6, // FREND1 Front end RX configuration.
195 0x10, // FREND0 Front end RX configuration.
196 0x18, // MCSM0 Main Radio Control State Machine configuration.
197 0x1D, // FOCCFG Frequency Offset Compensation Configuration.
198 0x1C, // BSCFG Bit synchronization Configuration.
199 0xC7, // AGCCTRL2 AGC control.
200 0x00, // AGCCTRL1 AGC control.
201 0xB2, // AGCCTRL0 AGC control.
202
203 0xEA, // FSCAL3 Frequency synthesizer calibration.
204 0x0A, // FSCAL2 Frequency synthesizer calibration.
205 0x00, // FSCAL1 Frequency synthesizer calibration.
206 0x11, // FSCAL0 Frequency synthesizer calibration.
207 0x59, // FSTEST Frequency synthesizer calibration.
208 0x88, // TEST2 Various test settings.
209 0x31, // TEST1 Various test settings.
210 0x0B, // TEST0 Various test settings.
211 0x06, // IOCFG2 GDO2 output pin configuration.
212 0x06, // IOCFG0D GDO0 output pin configuration. Refer to SmartRF?Studio User Manual for detailed p
-seudo register explanation.
213
214 0x04, // PKTCTRL1 Packet automation control.
215 0x05, // PKTCTRL0 Packet automation control.
216 0x00, // ADDR Device address.
217 0x0c // PKTLEN Packet length.
218 };
219
220 // PATABLE (0 dBm output power)
221
222
223 /*
224
225 const RF_SETTINGS rfSettings =
226 {
227 0x00,
228 0x0a, // FSCTRL1 Frequency synthesizer control.
229 0x00, // FSCTRL0 Frequency synthesizer control.
230
231 0x10, // FREQ2 Frequency control word, high byte.
232 0xB1, // FREQ1 Frequency control word, middle byte.
233 0x3b, // FREQ0 Frequency control word, low byte.
234
235 0x2b, //0x2D, // MDMCFG4 Modem configuration.
236 0xf8, //0x3B, // MDMCFG3 Modem configuration.
237 0x03, // MDMCFG2 Modem configuration.
C51 COMPILER V8.02 CC1100 11/15/2007 11:37:22 PAGE 5
238 0x22, // MDMCFG1 Modem configuration.
239 0xF8, // MDMCFG0 Modem configuration.
240
241 0x00, // CHANNR Channel number.
242 0x44, // DEVIATN Modem deviation setting (when FSK modulation is enabled).
243
244 0x56, // FREND1 Front end RX configuration.
245 0x10, // FREND0 Front end RX configuration.
246
247
248 0x18, // MCSM0 Main Radio Control State Machine configuration.
249
250 0x16, // FOCCFG Frequency Offset Compensation Configuration.
251
252 0x6C, // BSCFG Bit synchronization Configuration.
253
254 0x43, // AGCCTRL2 AGC control.
255 0x91, // AGCCTRL0 AGC control.
256
257 0xa9, // FSCAL3 Frequency ` calibration.
258 0x0a, // FSCAL2 Frequency synthesizer calibration.
259 0x11, // FSCAL0 Frequency synthesizer calibration.
260
261 0x59, // FSTEST Frequency synthesizer calibration.
262
263 0x88, // TEST2 Various test settings.
264 0x31, // TEST1 Various test settings.
265 0x0b, // TEST0 Various test settings.
266
267 0x24, // IOCFG2 GDO2 output pin configuration.
268 0x06, // IOCFG0D GDO0 output pin configuration. Refer to SmartRF?Studio User Manual for detailed pseu
-do register explanantion.
269
270 0x04, // PKTCTRL1 Packet automation control.
271 0x05, // PKTCTRL0 Packet automation control.
272
273 0x00, // ADDR Device address.
274 0x0c, // PKTLEN
275
276 };
277
278
279
280
281
282
283
284
285 const RF_SETTINGS rfSettings =
286 {
287 0x00,
288 0x0A, // FSCTRL1 Frequency synthesizer control.
289 0x00, // FSCTRL0 Frequency synthesizer control.
290 0x10, // FREQ2 Frequency control word, high byte.
291 0xB1, // FREQ1 Frequency control word, middle byte.
292 0x3b, // FREQ0 Frequency control word, low byte.
293 0x86, //0x2D, // MDMCFG4 Modem configuration.
294 0x83, //0x3B, // MDMCFG3 Modem configuration.
295 0x03, // MDMCFG2 Modem configuration.
296 0x22, // MDMCFG1 Modem configuration.
297 0xF8, // MDMCFG0 Modem configuration.
298
C51 COMPILER V8.02 CC1100 11/15/2007 11:37:22 PAGE 6
299 0x00, // CHANNR Channel number.
300 0x44, // DEVIATN Modem deviation setting (when FSK modulation is enabled).
301 0x56, // FREND1 Front end RX configuration.
302 0x10, // FREND0 Front end RX configuration.
303 0x18, // MCSM0 Main Radio Control State Machine configuration.
304 0x16, // FOCCFG Frequency Offset Compensation Configuration.
305 0x6C, // BSCFG Bit synchronization Configuration.
306 0x03, // AGCCTRL2 AGC control.
307 0x91, // AGCCTRL0 AGC control.
308 0xA9, // FSCAL3 Frequency ` calibration.
309
310 0x0a, // FSCAL2 Frequency synthesizer calibration.
311 0x11, // FSCAL0 Frequency synthesizer calibration.
312 0x59, // FSTEST Frequency synthesizer calibration.
313 0x88, // TEST2 Various test settings.
314 0x31, // TEST1 Various test settings.
315 0x0B, // TEST0 Various test settings.
316 0x24, // IOCFG2 GDO2 output pin configuration.
317 0x06, // IOCFG0D GDO0 output pin configuration. Refer to SmartRF?Studio User Manual for detailed pseu
-do register explanantion.
318 0x04, // PKTCTRL1 Packet automation control.
319 0x05, // PKTCTRL0 Packet automation control.
320
321 0x00, // ADDR Device address.
322 0x0c, // PKTLEN
323 };
324 */
325 #endif
MODULE INFORMATION: STATIC OVERLAYABLE
CODE SIZE = ---- ----
CONSTANT SIZE = ---- ----
XDATA SIZE = ---- ----
PDATA SIZE = ---- ----
DATA SIZE = 35 ----
IDATA SIZE = ---- ----
BIT SIZE = ---- ----
END OF MODULE INFORMATION.
C51 COMPILATION COMPLETE. 0 WARNING(S), 0 ERROR(S)
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