m66592-udc.h

linux下面gadget设备驱动

#define   M66592_DT_DEVICE			0x01
#define   M66592_DT_CONFIGURATION		0x02
#define   M66592_DT_STRING			0x03
#define   M66592_DT_INTERFACE			0x04
#define   M66592_DT_ENDPOINT			0x05
#define   M66592_DT_DEVICE_QUALIFIER		0x06
#define   M66592_DT_OTHER_SPEED_CONFIGURATION	0x07
#define   M66592_DT_INTERFACE_POWER		0x08
#define M66592_DT_INDEX				0x00FF
#define M66592_CONF_NUM				0x00FF
#define M66592_ALT_SET				0x00FF

#define M66592_USBINDEX			0x58
#define M66592_wIndex			0xFFFF	/* b15-0: wIndex */
#define M66592_TEST_SELECT		0xFF00	/* b15-b8: Test Mode */
#define   M66592_TEST_J			 0x0100	  /* Test_J */
#define   M66592_TEST_K			 0x0200	  /* Test_K */
#define   M66592_TEST_SE0_NAK		 0x0300	  /* Test_SE0_NAK */
#define   M66592_TEST_PACKET		 0x0400	  /* Test_Packet */
#define   M66592_TEST_FORCE_ENABLE	 0x0500	  /* Test_Force_Enable */
#define   M66592_TEST_STSelectors	 0x0600	  /* Standard test selectors */
#define   M66592_TEST_Reserved		 0x4000	  /* Reserved */
#define   M66592_TEST_VSTModes		 0xC000	  /* Vendor-specific tests */
#define M66592_EP_DIR			0x0080	/* b7: Endpoint Direction */
#define   M66592_EP_DIR_IN		 0x0080
#define   M66592_EP_DIR_OUT		 0x0000

#define M66592_USBLENG		0x5A
#define M66592_wLength		0xFFFF	/* b15-0: wLength */

#define M66592_DCPCFG		0x5C
#define M66592_CNTMD		0x0100	/* b8: Continuous transfer mode */
#define M66592_DIR		0x0010	/* b4: Control transfer DIR select */

#define M66592_DCPMAXP		0x5E
#define M66592_DEVSEL		0xC000	/* b15-14: Device address select */
#define   M66592_DEVICE_0	 0x0000		  /* Device address 0 */
#define   M66592_DEVICE_1	 0x4000		  /* Device address 1 */
#define   M66592_DEVICE_2	 0x8000		  /* Device address 2 */
#define   M66592_DEVICE_3	 0xC000		  /* Device address 3 */
#define M66592_MAXP		0x007F	/* b6-0: Maxpacket size of ep0 */

#define M66592_DCPCTR		0x60
#define M66592_BSTS		0x8000	/* b15: Buffer status */
#define M66592_SUREQ		0x4000	/* b14: Send USB request  */
#define M66592_SQCLR		0x0100	/* b8: Sequence toggle bit clear */
#define M66592_SQSET		0x0080	/* b7: Sequence toggle bit set */
#define M66592_SQMON		0x0040	/* b6: Sequence toggle bit monitor */
#define M66592_CCPL		0x0004	/* b2: control transfer complete */
#define M66592_PID		0x0003	/* b1-0: Response PID */
#define   M66592_PID_STALL	 0x0002		  /* STALL */
#define   M66592_PID_BUF	 0x0001		  /* BUF */
#define   M66592_PID_NAK	 0x0000		  /* NAK */

#define M66592_PIPESEL		0x64
#define M66592_PIPENM		0x0007	/* b2-0: Pipe select */
#define   M66592_PIPE0		 0x0000		  /* PIPE 0 */
#define   M66592_PIPE1		 0x0001		  /* PIPE 1 */
#define   M66592_PIPE2		 0x0002		  /* PIPE 2 */
#define   M66592_PIPE3		 0x0003		  /* PIPE 3 */
#define   M66592_PIPE4		 0x0004		  /* PIPE 4 */
#define   M66592_PIPE5		 0x0005		  /* PIPE 5 */
#define   M66592_PIPE6		 0x0006		  /* PIPE 6 */
#define   M66592_PIPE7		 0x0007		  /* PIPE 7 */

#define M66592_PIPECFG		0x66
#define M66592_TYP		0xC000	/* b15-14: Transfer type */
#define   M66592_ISO		 0xC000		  /* Isochronous */
#define   M66592_INT		 0x8000		  /* Interrupt */
#define   M66592_BULK		 0x4000		  /* Bulk */
#define M66592_BFRE		0x0400	/* b10: Buffer ready interrupt mode */
#define M66592_DBLB		0x0200	/* b9: Double buffer mode select */
#define M66592_CNTMD		0x0100	/* b8: Continuous transfer mode */
#define M66592_SHTNAK		0x0080	/* b7: Transfer end NAK */
#define M66592_DIR		0x0010	/* b4: Transfer direction select */
#define   M66592_DIR_H_OUT	 0x0010		  /* HOST OUT */
#define   M66592_DIR_P_IN	 0x0010		  /* PERI IN */
#define   M66592_DIR_H_IN	 0x0000		  /* HOST IN */
#define   M66592_DIR_P_OUT	 0x0000		  /* PERI OUT */
#define M66592_EPNUM		0x000F	/* b3-0: Eendpoint number select */
#define   M66592_EP1		 0x0001
#define   M66592_EP2		 0x0002
#define   M66592_EP3		 0x0003
#define   M66592_EP4		 0x0004
#define   M66592_EP5		 0x0005
#define   M66592_EP6		 0x0006
#define   M66592_EP7		 0x0007
#define   M66592_EP8		 0x0008
#define   M66592_EP9		 0x0009
#define   M66592_EP10		 0x000A
#define   M66592_EP11		 0x000B
#define   M66592_EP12		 0x000C
#define   M66592_EP13		 0x000D
#define   M66592_EP14		 0x000E
#define   M66592_EP15		 0x000F

#define M66592_PIPEBUF		0x68
#define M66592_BUFSIZE		0x7C00	/* b14-10: Pipe buffer size */
#define M66592_BUF_SIZE(x)	((((x) / 64) - 1) << 10)
#define M66592_BUFNMB		0x00FF	/* b7-0: Pipe buffer number */

#define M66592_PIPEMAXP		0x6A
#define M66592_MXPS		0x07FF	/* b10-0: Maxpacket size */

#define M66592_PIPEPERI		0x6C
#define M66592_IFIS		0x1000	/* b12: ISO in-buffer flush mode */
#define M66592_IITV		0x0007	/* b2-0: ISO interval */

#define M66592_PIPE1CTR		0x70
#define M66592_PIPE2CTR		0x72
#define M66592_PIPE3CTR		0x74
#define M66592_PIPE4CTR		0x76
#define M66592_PIPE5CTR		0x78
#define M66592_PIPE6CTR		0x7A
#define M66592_PIPE7CTR		0x7C
#define M66592_BSTS		0x8000	/* b15: Buffer status */
#define M66592_INBUFM		0x4000	/* b14: IN buffer monitor (PIPE 1-5) */
#define M66592_ACLRM		0x0200	/* b9: Out buffer auto clear mode */
#define M66592_SQCLR		0x0100	/* b8: Sequence toggle bit clear */
#define M66592_SQSET		0x0080	/* b7: Sequence toggle bit set */
#define M66592_SQMON		0x0040	/* b6: Sequence toggle bit monitor */
#define M66592_PID		0x0003	/* b1-0: Response PID */

#define M66592_INVALID_REG	0x7E


#define get_pipectr_addr(pipenum)	(M66592_PIPE1CTR + (pipenum - 1) * 2)

#define M66592_MAX_SAMPLING	10

#define M66592_MAX_NUM_PIPE	8
#define M66592_MAX_NUM_BULK	3
#define M66592_MAX_NUM_ISOC	2
#define M66592_MAX_NUM_INT	2

#define M66592_BASE_PIPENUM_BULK	3
#define M66592_BASE_PIPENUM_ISOC	1
#define M66592_BASE_PIPENUM_INT		6

#define M66592_BASE_BUFNUM	6
#define M66592_MAX_BUFNUM	0x4F

struct m66592_pipe_info {
	u16	pipe;
	u16	epnum;
	u16	maxpacket;
	u16	type;
	u16	interval;
	u16	dir_in;
};

struct m66592_request {
	struct usb_request	req;
	struct list_head	queue;
};

struct m66592_ep {
	struct usb_ep		ep;
	struct m66592		*m66592;

	struct list_head	queue;
	unsigned		busy:1;
	unsigned		internal_ccpl:1;	/* use only control */

	/* this member can able to after m66592_enable */
	unsigned		use_dma:1;
	u16			pipenum;
	u16			type;
	const struct usb_endpoint_descriptor	*desc;
	/* register address */
	unsigned long		fifoaddr;
	unsigned long		fifosel;
	unsigned long		fifoctr;
	unsigned long		fifotrn;
	unsigned long		pipectr;
};

struct m66592 {
	spinlock_t		lock;
	void __iomem		*reg;

	struct usb_gadget		gadget;
	struct usb_gadget_driver	*driver;

	struct m66592_ep	ep[M66592_MAX_NUM_PIPE];
	struct m66592_ep	*pipenum2ep[M66592_MAX_NUM_PIPE];
	struct m66592_ep	*epaddr2ep[16];

	struct usb_request	*ep0_req;	/* for internal request */
	u16			ep0_data;	/* for internal request */

	struct timer_list	timer;

	u16			old_vbus;
	int			scount;

	int			old_dvsq;

	/* pipe config */
	int bulk;
	int interrupt;
	int isochronous;
	int num_dma;
	int bi_bufnum;	/* bulk and isochronous's bufnum */
};

#define gadget_to_m66592(_gadget) container_of(_gadget, struct m66592, gadget)
#define m66592_to_gadget(m66592) (&m66592->gadget)

#define is_bulk_pipe(pipenum)	\
	((pipenum >= M66592_BASE_PIPENUM_BULK) && \
	 (pipenum < (M66592_BASE_PIPENUM_BULK + M66592_MAX_NUM_BULK)))
#define is_interrupt_pipe(pipenum)	\
	((pipenum >= M66592_BASE_PIPENUM_INT) && \
	 (pipenum < (M66592_BASE_PIPENUM_INT + M66592_MAX_NUM_INT)))
#define is_isoc_pipe(pipenum)	\
	((pipenum >= M66592_BASE_PIPENUM_ISOC) && \
	 (pipenum < (M66592_BASE_PIPENUM_ISOC + M66592_MAX_NUM_ISOC)))

#define enable_irq_ready(m66592, pipenum)	\
	enable_pipe_irq(m66592, pipenum, M66592_BRDYENB)
#define disable_irq_ready(m66592, pipenum)	\
	disable_pipe_irq(m66592, pipenum, M66592_BRDYENB)
#define enable_irq_empty(m66592, pipenum)	\
	enable_pipe_irq(m66592, pipenum, M66592_BEMPENB)
#define disable_irq_empty(m66592, pipenum)	\
	disable_pipe_irq(m66592, pipenum, M66592_BEMPENB)
#define enable_irq_nrdy(m66592, pipenum)	\
	enable_pipe_irq(m66592, pipenum, M66592_NRDYENB)
#define disable_irq_nrdy(m66592, pipenum)	\
	disable_pipe_irq(m66592, pipenum, M66592_NRDYENB)

/*-------------------------------------------------------------------------*/
static inline u16 m66592_read(struct m66592 *m66592, unsigned long offset)
{
	return inw((unsigned long)m66592->reg + offset);
}

static inline void m66592_read_fifo(struct m66592 *m66592,
		unsigned long offset,
		void *buf, unsigned long len)
{
	unsigned long fifoaddr = (unsigned long)m66592->reg + offset;

	len = (len + 1) / 2;
	insw(fifoaddr, buf, len);
}

static inline void m66592_write(struct m66592 *m66592, u16 val,
				unsigned long offset)
{
	outw(val, (unsigned long)m66592->reg + offset);
}

static inline void m66592_write_fifo(struct m66592 *m66592,
		unsigned long offset,
		void *buf, unsigned long len)
{
	unsigned long fifoaddr = (unsigned long)m66592->reg + offset;
	unsigned long odd = len & 0x0001;

	len = len / 2;
	outsw(fifoaddr, buf, len);
	if (odd) {
		unsigned char *p = buf + len*2;
		outb(*p, fifoaddr);
	}
}

static inline void m66592_mdfy(struct m66592 *m66592, u16 val, u16 pat,
		unsigned long offset)
{
	u16 tmp;
	tmp = m66592_read(m66592, offset);
	tmp = tmp & (~pat);
	tmp = tmp | val;
	m66592_write(m66592, tmp, offset);
}

#define m66592_bclr(m66592, val, offset)	\
			m66592_mdfy(m66592, 0, val, offset)
#define m66592_bset(m66592, val, offset)	\
			m66592_mdfy(m66592, val, 0, offset)

#endif	/* ifndef __M66592_UDC_H__ */