amd5536udc.h

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/* IN data, Status dword */
#define UDC_DMA_IN_STS_TXBYTES_MASK		0x0000ffff
#define UDC_DMA_IN_STS_TXBYTES_OFS		0
#define	UDC_DMA_IN_STS_FRAMENUM_MASK		0x07ff0000
#define UDC_DMA_IN_STS_FRAMENUM_OFS		0
#define UDC_DMA_IN_STS_L			27
#define UDC_DMA_IN_STS_TX_MASK			0x30000000
#define UDC_DMA_IN_STS_TX_OFS			28
#define UDC_DMA_IN_STS_BS_MASK			0xc0000000
#define UDC_DMA_IN_STS_BS_OFS			30
#define UDC_DMA_IN_STS_BS_HOST_READY		0
#define UDC_DMA_IN_STS_BS_DMA_BUSY		1
#define UDC_DMA_IN_STS_BS_DMA_DONE		2
#define UDC_DMA_IN_STS_BS_HOST_BUSY		3
/* OUT data, Status dword */
#define UDC_DMA_OUT_STS_RXBYTES_MASK		0x0000ffff
#define UDC_DMA_OUT_STS_RXBYTES_OFS		0
#define UDC_DMA_OUT_STS_FRAMENUM_MASK		0x07ff0000
#define UDC_DMA_OUT_STS_FRAMENUM_OFS		0
#define UDC_DMA_OUT_STS_L			27
#define UDC_DMA_OUT_STS_RX_MASK			0x30000000
#define UDC_DMA_OUT_STS_RX_OFS			28
#define UDC_DMA_OUT_STS_BS_MASK			0xc0000000
#define UDC_DMA_OUT_STS_BS_OFS			30
#define UDC_DMA_OUT_STS_BS_HOST_READY		0
#define UDC_DMA_OUT_STS_BS_DMA_BUSY		1
#define UDC_DMA_OUT_STS_BS_DMA_DONE		2
#define UDC_DMA_OUT_STS_BS_HOST_BUSY		3
/* max ep0in packet */
#define UDC_EP0IN_MAXPACKET			1000
/* max dma packet */
#define UDC_DMA_MAXPACKET			65536

/* un-usable DMA address */
#define DMA_DONT_USE				(~(dma_addr_t) 0 )

/* other Endpoint register addresses and values-----------------------------*/
#define UDC_EP_SUBPTR_ADDR			0x10
#define UDC_EP_DESPTR_ADDR			0x14
#define UDC_EP_WRITE_CONFIRM_ADDR		0x1c

/* EP number as layouted in AHB space */
#define UDC_EP_NUM				32
#define UDC_EPIN_NUM				16
#define UDC_EPIN_NUM_USED			5
#define UDC_EPOUT_NUM				16
/* EP number of EP's really used = EP0 + 8 data EP's */
#define UDC_USED_EP_NUM				9
/* UDC CSR regs are aligned but AHB regs not - offset for OUT EP's */
#define UDC_CSR_EP_OUT_IX_OFS			12

#define UDC_EP0OUT_IX				16
#define UDC_EP0IN_IX				0

/* Rx fifo address and size = 1k -------------------------------------------*/
#define UDC_RXFIFO_ADDR				0x800
#define UDC_RXFIFO_SIZE				0x400

/* Tx fifo address and size = 1.5k -----------------------------------------*/
#define UDC_TXFIFO_ADDR				0xc00
#define UDC_TXFIFO_SIZE				0x600

/* default data endpoints --------------------------------------------------*/
#define UDC_EPIN_STATUS_IX			1
#define UDC_EPIN_IX				2
#define UDC_EPOUT_IX				18

/* general constants -------------------------------------------------------*/
#define UDC_DWORD_BYTES				4
#define UDC_BITS_PER_BYTE_SHIFT			3
#define UDC_BYTE_MASK				0xff
#define UDC_BITS_PER_BYTE			8

/*---------------------------------------------------------------------------*/
/* UDC CSR's */
struct udc_csrs {

	/* sca - setup command address */
	u32 sca;

	/* ep ne's */
	u32 ne[UDC_USED_EP_NUM];
} __attribute__ ((packed));

/* AHB subsystem CSR registers */
struct udc_regs {

	/* device configuration */
	u32 cfg;

	/* device control */
	u32 ctl;

	/* device status */
	u32 sts;

	/* device interrupt */
	u32 irqsts;

	/* device interrupt mask */
	u32 irqmsk;

	/* endpoint interrupt */
	u32 ep_irqsts;

	/* endpoint interrupt mask */
	u32 ep_irqmsk;
} __attribute__ ((packed));

/* endpoint specific registers */
struct udc_ep_regs {

	/* endpoint control */
	u32 ctl;

	/* endpoint status */
	u32 sts;

	/* endpoint buffer size in/ receive packet frame number out */
	u32 bufin_framenum;

	/* endpoint buffer size out/max packet size */
	u32 bufout_maxpkt;

	/* endpoint setup buffer pointer */
	u32 subptr;

	/* endpoint data descriptor pointer */
	u32 desptr;

	/* reserverd */
	u32 reserved;

	/* write/read confirmation */
	u32 confirm;

} __attribute__ ((packed));

/* control data DMA desc */
struct udc_stp_dma {
	/* status quadlet */
	u32	status;
	/* reserved */
	u32	_reserved;
	/* first setup word */
	u32	data12;
	/* second setup word */
	u32	data34;
} __attribute__ ((aligned (16)));

/* normal data DMA desc */
struct udc_data_dma {
	/* status quadlet */
	u32	status;
	/* reserved */
	u32	_reserved;
	/* buffer pointer */
	u32	bufptr;
	/* next descriptor pointer */
	u32	next;
} __attribute__ ((aligned (16)));

/* request packet */
struct udc_request {
	/* embedded gadget ep */
	struct usb_request		req;

	/* flags */
	unsigned			dma_going : 1,
					dma_mapping : 1,
					dma_done : 1;
	/* phys. address */
	dma_addr_t			td_phys;
	/* first dma desc. of chain */
	struct udc_data_dma		*td_data;
	/* last dma desc. of chain */
	struct udc_data_dma		*td_data_last;
	struct list_head		queue;

	/* chain length */
	unsigned			chain_len;

};

/* UDC specific endpoint parameters */
struct udc_ep {
	struct usb_ep			ep;
	struct udc_ep_regs __iomem	*regs;
	u32 __iomem			*txfifo;
	u32 __iomem			*dma;
	dma_addr_t			td_phys;
	dma_addr_t			td_stp_dma;
	struct udc_stp_dma		*td_stp;
	struct udc_data_dma		*td;
	/* temp request */
	struct udc_request		*req;
	unsigned			req_used;
	unsigned			req_completed;
	/* dummy DMA desc for BNA dummy */
	struct udc_request		*bna_dummy_req;
	unsigned			bna_occurred;

	/* NAK state */
	unsigned			naking;

	struct udc			*dev;

	/* queue for requests */
	struct list_head		queue;
	const struct usb_endpoint_descriptor	*desc;
	unsigned			halted;
	unsigned			cancel_transfer;
	unsigned			num : 5,
					fifo_depth : 14,
					in : 1;
};

/* device struct */
struct udc {
	struct usb_gadget		gadget;
	spinlock_t			lock;	/* protects all state */
	/* all endpoints */
	struct udc_ep			ep[UDC_EP_NUM];
	struct usb_gadget_driver	*driver;
	/* operational flags */
	unsigned			active : 1,
					stall_ep0in : 1,
					waiting_zlp_ack_ep0in : 1,
					set_cfg_not_acked : 1,
					irq_registered : 1,
					data_ep_enabled : 1,
					data_ep_queued : 1,
					mem_region : 1,
					sys_suspended : 1,
					connected;

	u16				chiprev;

	/* registers */
	struct pci_dev			*pdev;
	struct udc_csrs __iomem		*csr;
	struct udc_regs __iomem		*regs;
	struct udc_ep_regs __iomem	*ep_regs;
	u32 __iomem			*rxfifo;
	u32 __iomem			*txfifo;

	/* DMA desc pools */
	struct pci_pool			*data_requests;
	struct pci_pool			*stp_requests;

	/* device data */
	unsigned long			phys_addr;
	void __iomem			*virt_addr;
	unsigned			irq;

	/* states */
	u16				cur_config;
	u16				cur_intf;
	u16				cur_alt;
};

/* setup request data */
union udc_setup_data {
	u32			data[2];
	struct usb_ctrlrequest	request;
};

/*
 *---------------------------------------------------------------------------
 * SET and GET bitfields in u32 values
 * via constants for mask/offset:
 * <bit_field_stub_name> is the text between
 * UDC_ and _MASK|_OFS of appropiate
 * constant
 *
 * set bitfield value in u32 u32Val
 */
#define AMD_ADDBITS(u32Val, bitfield_val, bitfield_stub_name)		\
	(((u32Val) & (((u32) ~((u32) bitfield_stub_name##_MASK))))	\
	| (((bitfield_val) << ((u32) bitfield_stub_name##_OFS))		\
		& ((u32) bitfield_stub_name##_MASK)))

/*
 * set bitfield value in zero-initialized u32 u32Val
 * => bitfield bits in u32Val are all zero
 */
#define AMD_INIT_SETBITS(u32Val, bitfield_val, bitfield_stub_name)	\
	((u32Val)							\
	| (((bitfield_val) << ((u32) bitfield_stub_name##_OFS))		\
		& ((u32) bitfield_stub_name##_MASK)))

/* get bitfield value from u32 u32Val */
#define AMD_GETBITS(u32Val, bitfield_stub_name)				\
	((u32Val & ((u32) bitfield_stub_name##_MASK))			\
		>> ((u32) bitfield_stub_name##_OFS))

/* SET and GET bits in u32 values ------------------------------------------*/
#define AMD_BIT(bit_stub_name) (1 << bit_stub_name)
#define AMD_UNMASK_BIT(bit_stub_name) (~AMD_BIT(bit_stub_name))
#define AMD_CLEAR_BIT(bit_stub_name) (~AMD_BIT(bit_stub_name))

/* debug macros ------------------------------------------------------------*/

#define DBG(udc , args...)	dev_dbg(&(udc)->pdev->dev, args)

#ifdef UDC_VERBOSE
#define VDBG			DBG
#else
#define VDBG(udc , args...)	do {} while (0)
#endif

#endif /* #ifdef AMD5536UDC_H */