amd5536udc.h

linux下面gadget设备驱动

/*
 * amd5536.h -- header for AMD 5536 UDC high/full speed USB device controller
 *
 * Copyright (C) 2007 AMD (http://www.amd.com)
 * Author: Thomas Dahlmann
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */

#ifndef AMD5536UDC_H
#define AMD5536UDC_H

/* various constants */
#define UDC_RDE_TIMER_SECONDS		1
#define UDC_RDE_TIMER_DIV		10
#define UDC_POLLSTALL_TIMER_USECONDS	500

/* Hs AMD5536 chip rev. */
#define UDC_HSA0_REV 1
#define UDC_HSB1_REV 2

/*
 * SETUP usb commands
 * needed, because some SETUP's are handled in hw, but must be passed to
 * gadget driver above
 * SET_CONFIG
 */
#define UDC_SETCONFIG_DWORD0			0x00000900
#define UDC_SETCONFIG_DWORD0_VALUE_MASK		0xffff0000
#define UDC_SETCONFIG_DWORD0_VALUE_OFS		16

#define UDC_SETCONFIG_DWORD1			0x00000000

/* SET_INTERFACE */
#define UDC_SETINTF_DWORD0			0x00000b00
#define UDC_SETINTF_DWORD0_ALT_MASK		0xffff0000
#define UDC_SETINTF_DWORD0_ALT_OFS		16

#define UDC_SETINTF_DWORD1			0x00000000
#define UDC_SETINTF_DWORD1_INTF_MASK		0x0000ffff
#define UDC_SETINTF_DWORD1_INTF_OFS		0

/* Mass storage reset */
#define UDC_MSCRES_DWORD0			0x0000ff21
#define UDC_MSCRES_DWORD1			0x00000000

/* Global CSR's -------------------------------------------------------------*/
#define UDC_CSR_ADDR				0x500

/* EP NE bits */
/* EP number */
#define UDC_CSR_NE_NUM_MASK			0x0000000f
#define UDC_CSR_NE_NUM_OFS			0
/* EP direction */
#define UDC_CSR_NE_DIR_MASK			0x00000010
#define UDC_CSR_NE_DIR_OFS			4
/* EP type */
#define UDC_CSR_NE_TYPE_MASK			0x00000060
#define UDC_CSR_NE_TYPE_OFS			5
/* EP config number */
#define UDC_CSR_NE_CFG_MASK			0x00000780
#define UDC_CSR_NE_CFG_OFS			7
/* EP interface number */
#define UDC_CSR_NE_INTF_MASK			0x00007800
#define UDC_CSR_NE_INTF_OFS			11
/* EP alt setting */
#define UDC_CSR_NE_ALT_MASK			0x00078000
#define UDC_CSR_NE_ALT_OFS			15

/* max pkt */
#define UDC_CSR_NE_MAX_PKT_MASK			0x3ff80000
#define UDC_CSR_NE_MAX_PKT_OFS			19

/* Device Config Register ---------------------------------------------------*/
#define UDC_DEVCFG_ADDR				0x400

#define UDC_DEVCFG_SOFTRESET			31
#define UDC_DEVCFG_HNPSFEN			30
#define UDC_DEVCFG_DMARST			29
#define UDC_DEVCFG_SET_DESC			18
#define UDC_DEVCFG_CSR_PRG			17
#define UDC_DEVCFG_STATUS			7
#define UDC_DEVCFG_DIR				6
#define UDC_DEVCFG_PI				5
#define UDC_DEVCFG_SS				4
#define UDC_DEVCFG_SP				3
#define UDC_DEVCFG_RWKP				2

#define UDC_DEVCFG_SPD_MASK			0x3
#define UDC_DEVCFG_SPD_OFS			0
#define UDC_DEVCFG_SPD_HS			0x0
#define UDC_DEVCFG_SPD_FS			0x1
#define UDC_DEVCFG_SPD_LS			0x2
/*#define UDC_DEVCFG_SPD_FS			0x3*/


/* Device Control Register --------------------------------------------------*/
#define UDC_DEVCTL_ADDR				0x404

#define UDC_DEVCTL_THLEN_MASK			0xff000000
#define UDC_DEVCTL_THLEN_OFS			24

#define UDC_DEVCTL_BRLEN_MASK			0x00ff0000
#define UDC_DEVCTL_BRLEN_OFS			16

#define UDC_DEVCTL_CSR_DONE			13
#define UDC_DEVCTL_DEVNAK			12
#define UDC_DEVCTL_SD				10
#define UDC_DEVCTL_MODE				9
#define UDC_DEVCTL_BREN				8
#define UDC_DEVCTL_THE				7
#define UDC_DEVCTL_BF				6
#define UDC_DEVCTL_BE				5
#define UDC_DEVCTL_DU				4
#define UDC_DEVCTL_TDE				3
#define UDC_DEVCTL_RDE				2
#define UDC_DEVCTL_RES				0


/* Device Status Register ---------------------------------------------------*/
#define UDC_DEVSTS_ADDR				0x408

#define UDC_DEVSTS_TS_MASK			0xfffc0000
#define UDC_DEVSTS_TS_OFS			18

#define UDC_DEVSTS_SESSVLD			17
#define UDC_DEVSTS_PHY_ERROR			16
#define UDC_DEVSTS_RXFIFO_EMPTY			15

#define UDC_DEVSTS_ENUM_SPEED_MASK		0x00006000
#define UDC_DEVSTS_ENUM_SPEED_OFS		13
#define UDC_DEVSTS_ENUM_SPEED_FULL		1
#define UDC_DEVSTS_ENUM_SPEED_HIGH		0

#define UDC_DEVSTS_SUSP				12

#define UDC_DEVSTS_ALT_MASK			0x00000f00
#define UDC_DEVSTS_ALT_OFS			8

#define UDC_DEVSTS_INTF_MASK			0x000000f0
#define UDC_DEVSTS_INTF_OFS			4

#define UDC_DEVSTS_CFG_MASK			0x0000000f
#define UDC_DEVSTS_CFG_OFS			0


/* Device Interrupt Register ------------------------------------------------*/
#define UDC_DEVINT_ADDR				0x40c

#define UDC_DEVINT_SVC				7
#define UDC_DEVINT_ENUM				6
#define UDC_DEVINT_SOF				5
#define UDC_DEVINT_US				4
#define UDC_DEVINT_UR				3
#define UDC_DEVINT_ES				2
#define UDC_DEVINT_SI				1
#define UDC_DEVINT_SC				0

/* Device Interrupt Mask Register -------------------------------------------*/
#define UDC_DEVINT_MSK_ADDR			0x410

#define UDC_DEVINT_MSK				0x7f

/* Endpoint Interrupt Register ----------------------------------------------*/
#define UDC_EPINT_ADDR				0x414

#define UDC_EPINT_OUT_MASK			0xffff0000
#define UDC_EPINT_OUT_OFS			16
#define UDC_EPINT_IN_MASK			0x0000ffff
#define UDC_EPINT_IN_OFS			0

#define UDC_EPINT_IN_EP0			0
#define UDC_EPINT_IN_EP1			1
#define UDC_EPINT_IN_EP2			2
#define UDC_EPINT_IN_EP3			3
#define UDC_EPINT_OUT_EP0			16
#define UDC_EPINT_OUT_EP1			17
#define UDC_EPINT_OUT_EP2			18
#define UDC_EPINT_OUT_EP3			19

#define UDC_EPINT_EP0_ENABLE_MSK		0x001e001e

/* Endpoint Interrupt Mask Register -----------------------------------------*/
#define UDC_EPINT_MSK_ADDR			0x418

#define UDC_EPINT_OUT_MSK_MASK			0xffff0000
#define UDC_EPINT_OUT_MSK_OFS			16
#define UDC_EPINT_IN_MSK_MASK			0x0000ffff
#define UDC_EPINT_IN_MSK_OFS			0

#define UDC_EPINT_MSK_DISABLE_ALL		0xffffffff
/* mask non-EP0 endpoints */
#define UDC_EPDATAINT_MSK_DISABLE		0xfffefffe
/* mask all dev interrupts */
#define UDC_DEV_MSK_DISABLE			0x7f

/* Endpoint-specific CSR's --------------------------------------------------*/
#define UDC_EPREGS_ADDR				0x0
#define UDC_EPIN_REGS_ADDR			0x0
#define UDC_EPOUT_REGS_ADDR			0x200

#define UDC_EPCTL_ADDR				0x0

#define UDC_EPCTL_RRDY				9
#define UDC_EPCTL_CNAK				8
#define UDC_EPCTL_SNAK				7
#define UDC_EPCTL_NAK				6

#define UDC_EPCTL_ET_MASK			0x00000030
#define UDC_EPCTL_ET_OFS			4
#define UDC_EPCTL_ET_CONTROL			0
#define UDC_EPCTL_ET_ISO			1
#define UDC_EPCTL_ET_BULK			2
#define UDC_EPCTL_ET_INTERRUPT			3

#define UDC_EPCTL_P				3
#define UDC_EPCTL_SN				2
#define UDC_EPCTL_F				1
#define UDC_EPCTL_S				0

/* Endpoint Status Registers ------------------------------------------------*/
#define UDC_EPSTS_ADDR				0x4

#define UDC_EPSTS_RX_PKT_SIZE_MASK		0x007ff800
#define UDC_EPSTS_RX_PKT_SIZE_OFS		11

#define UDC_EPSTS_TDC				10
#define UDC_EPSTS_HE				9
#define UDC_EPSTS_BNA				7
#define UDC_EPSTS_IN				6

#define UDC_EPSTS_OUT_MASK			0x00000030
#define UDC_EPSTS_OUT_OFS			4
#define UDC_EPSTS_OUT_DATA			1
#define UDC_EPSTS_OUT_DATA_CLEAR		0x10
#define UDC_EPSTS_OUT_SETUP			2
#define UDC_EPSTS_OUT_SETUP_CLEAR		0x20
#define UDC_EPSTS_OUT_CLEAR			0x30

/* Endpoint Buffer Size IN/ Receive Packet Frame Number OUT Registers ------*/
#define UDC_EPIN_BUFF_SIZE_ADDR			0x8
#define UDC_EPOUT_FRAME_NUMBER_ADDR		0x8

#define UDC_EPIN_BUFF_SIZE_MASK			0x0000ffff
#define UDC_EPIN_BUFF_SIZE_OFS			0
/* EP0in txfifo = 128 bytes*/
#define UDC_EPIN0_BUFF_SIZE			32
/* EP0in fullspeed txfifo = 128 bytes*/
#define UDC_FS_EPIN0_BUFF_SIZE			32

/* fifo size mult = fifo size / max packet */
#define UDC_EPIN_BUFF_SIZE_MULT			2

/* EPin data fifo size = 1024 bytes DOUBLE BUFFERING */
#define UDC_EPIN_BUFF_SIZE			256
/* EPin small INT data fifo size = 128 bytes */
#define UDC_EPIN_SMALLINT_BUFF_SIZE		32

/* EPin fullspeed data fifo size = 128 bytes DOUBLE BUFFERING */
#define UDC_FS_EPIN_BUFF_SIZE			32

#define UDC_EPOUT_FRAME_NUMBER_MASK		0x0000ffff
#define UDC_EPOUT_FRAME_NUMBER_OFS		0

/* Endpoint Buffer Size OUT/Max Packet Size Registers -----------------------*/
#define UDC_EPOUT_BUFF_SIZE_ADDR		0x0c
#define UDC_EP_MAX_PKT_SIZE_ADDR		0x0c

#define UDC_EPOUT_BUFF_SIZE_MASK		0xffff0000
#define UDC_EPOUT_BUFF_SIZE_OFS			16
#define UDC_EP_MAX_PKT_SIZE_MASK		0x0000ffff
#define UDC_EP_MAX_PKT_SIZE_OFS			0
/* EP0in max packet size = 64 bytes */
#define UDC_EP0IN_MAX_PKT_SIZE			64
/* EP0out max packet size = 64 bytes */
#define UDC_EP0OUT_MAX_PKT_SIZE			64
/* EP0in fullspeed max packet size = 64 bytes */
#define UDC_FS_EP0IN_MAX_PKT_SIZE		64
/* EP0out fullspeed max packet size = 64 bytes */
#define UDC_FS_EP0OUT_MAX_PKT_SIZE		64

/*
 * Endpoint dma descriptors ------------------------------------------------
 *
 * Setup data, Status dword
 */
#define UDC_DMA_STP_STS_CFG_MASK		0x0fff0000
#define UDC_DMA_STP_STS_CFG_OFS			16
#define UDC_DMA_STP_STS_CFG_ALT_MASK		0x000f0000
#define UDC_DMA_STP_STS_CFG_ALT_OFS		16
#define UDC_DMA_STP_STS_CFG_INTF_MASK		0x00f00000
#define UDC_DMA_STP_STS_CFG_INTF_OFS		20
#define UDC_DMA_STP_STS_CFG_NUM_MASK		0x0f000000
#define UDC_DMA_STP_STS_CFG_NUM_OFS		24
#define UDC_DMA_STP_STS_RX_MASK			0x30000000
#define UDC_DMA_STP_STS_RX_OFS			28
#define UDC_DMA_STP_STS_BS_MASK			0xc0000000
#define UDC_DMA_STP_STS_BS_OFS			30
#define UDC_DMA_STP_STS_BS_HOST_READY		0
#define UDC_DMA_STP_STS_BS_DMA_BUSY		1
#define UDC_DMA_STP_STS_BS_DMA_DONE		2
#define UDC_DMA_STP_STS_BS_HOST_BUSY		3