📄 main.txt
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; generated by ARM/Thumb C/C++ Compiler with , RVCT3.1 [Build 919] for uVision
; commandline ArmCC [--debug -c --asm --interleave -o..\Obj\main.o --depend=..\Obj\main.d --device=DARMSTM --apcs=interwork -O0 -I..\..\..\..\..\INC\ST\STM32F10x -IC:\Keil\ARM\INC\ST\STM32F10x -DVECT_TAB_FLASH --omf_browse=..\Obj\main.crf main.c]
THUMB
AREA ||.text||, CODE, READONLY, ALIGN=2
NVIC_Configuration PROC
;;;194 void NVIC_Configuration(void)
;;;195 {
000000 b510 PUSH {r4,lr}
;;;196 #ifdef VECT_TAB_RAM
;;;197 /* Set the Vector Table base location at 0x20000000 */
;;;198 NVIC_SetVectorTable(NVIC_VectTab_RAM, 0x0);
;;;199 #else /* VECT_TAB_FLASH */
;;;200 /* Set the Vector Table base location at 0x08000000 */
;;;201 NVIC_SetVectorTable(NVIC_VectTab_FLASH, 0x0);
000002 2100 MOVS r1,#0
000004 f04ff04f MOV r0,#0x8000000
000008 f7fff7ff BL NVIC_SetVectorTable
;;;202 #endif
;;;203 }
00000c bd10 POP {r4,pc}
;;;204
ENDP
GPIO_Configuration PROC
;;;174 void GPIO_Configuration(void)
;;;175 {
00000e b508 PUSH {r3,lr}
;;;176 GPIO_InitTypeDef GPIO_InitStructure;
;;;177
;;;178 /* Enable GPIOC clock */
;;;179 RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOC , ENABLE);
000010 2101 MOVS r1,#1
000012 2010 MOVS r0,#0x10
000014 f7fff7ff BL RCC_APB2PeriphClockCmd
;;;180
;;;181 /* Configure Pc.04 (ADC Channel14) as analog input */
;;;182 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_4;
000018 2010 MOVS r0,#0x10
00001a f8adf8ad STRH r0,[sp,#0]
;;;183 GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AIN;
00001e 2000 MOVS r0,#0
000020 f88df88d STRB r0,[sp,#3]
;;;184 GPIO_Init(GPIOC, &GPIO_InitStructure);
000024 4669 MOV r1,sp
000026 4849 LDR r0,|L1.332|
000028 f7fff7ff BL GPIO_Init
;;;185 }
00002c bd08 POP {r3,pc}
;;;186
ENDP
RCC_Configuration PROC
;;;113 void RCC_Configuration(void)
;;;114 {
00002e b510 PUSH {r4,lr}
;;;115 /* RCC system reset(for debug purpose) */
;;;116 RCC_DeInit();
000030 f7fff7ff BL RCC_DeInit
;;;117
;;;118 /* Enable HSE */
;;;119 RCC_HSEConfig(RCC_HSE_ON);
000034 f44ff44f MOV r0,#0x10000
000038 f7fff7ff BL RCC_HSEConfig
;;;120
;;;121 /* Wait till HSE is ready */
;;;122 while(RCC_GetFlagStatus(RCC_FLAG_HSERDY) == RESET)
00003c bf00 NOP
|L1.62|
00003e 2031 MOVS r0,#0x31
000040 f7fff7ff BL RCC_GetFlagStatus
000044 2800 CMP r0,#0
000046 d0fa BEQ |L1.62|
;;;123 {
;;;124 }
;;;125
;;;126 /* HCLK = SYSCLK */
;;;127 RCC_HCLKConfig(RCC_SYSCLK_Div1);
000048 2000 MOVS r0,#0
00004a f7fff7ff BL RCC_HCLKConfig
;;;128
;;;129 /* PCLK2 = HCLK */
;;;130 RCC_PCLK2Config(RCC_HCLK_Div1);
00004e 2000 MOVS r0,#0
000050 f7fff7ff BL RCC_PCLK2Config
;;;131
;;;132 /* PCLK1 = HCLK/2 */
;;;133 RCC_PCLK1Config(RCC_HCLK_Div2);
000054 f44ff44f MOV r0,#0x400
000058 f7fff7ff BL RCC_PCLK1Config
;;;134
;;;135 /* ADCCLK = PCLK2/4 */
;;;136 RCC_ADCCLKConfig(RCC_PCLK2_Div4);
00005c f44ff44f MOV r0,#0x4000
000060 f7fff7ff BL RCC_ADCCLKConfig
;;;137
;;;138 /* Flash 1 wait state */
;;;139 *(vu32 *)0x40022000 = 0x01;
000064 2001 MOVS r0,#1
000066 493a LDR r1,|L1.336|
000068 6008 STR r0,[r1,#0]
;;;140
;;;141 /* PLLCLK = 8MHz * 7 = 56 MHz */
;;;142 RCC_PLLConfig(RCC_PLLSource_HSE_Div1, RCC_PLLMul_7);
00006a f44ff44f MOV r1,#0x140000
00006e 0400 LSLS r0,r0,#16
000070 f7fff7ff BL RCC_PLLConfig
;;;143
;;;144 /* Enable PLL */
;;;145 RCC_PLLCmd(ENABLE);
000074 2001 MOVS r0,#1
000076 f7fff7ff BL RCC_PLLCmd
;;;146
;;;147 /* Wait till PLL is ready */
;;;148 while(RCC_GetFlagStatus(RCC_FLAG_PLLRDY) == RESET)
00007a bf00 NOP
|L1.124|
00007c 2039 MOVS r0,#0x39
00007e f7fff7ff BL RCC_GetFlagStatus
000082 2800 CMP r0,#0
000084 d0fa BEQ |L1.124|
;;;149 {
;;;150 }
;;;151
;;;152 /* Select PLL as system clock source */
;;;153 RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK);
000086 2002 MOVS r0,#2
000088 f7fff7ff BL RCC_SYSCLKConfig
;;;154
;;;155 /* Wait till PLL is used as system clock source */
;;;156 while(RCC_GetSYSCLKSource() != 0x08)
00008c bf00 NOP
|L1.142|
00008e f7fff7ff BL RCC_GetSYSCLKSource
000092 2808 CMP r0,#8
000094 d1fb BNE |L1.142|
;;;157 {
;;;158 }
;;;159
;;;160 /* Enable DMA clock */
;;;161 RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA, ENABLE);
000096 2101 MOVS r1,#1
000098 4608 MOV r0,r1
00009a f7fff7ff BL RCC_AHBPeriphClockCmd
;;;162
;;;163 /* Enable ADC1 clock */
;;;164 RCC_APB2PeriphClockCmd(RCC_APB2Periph_ADC1, ENABLE);
00009e 2101 MOVS r1,#1
0000a0 0248 LSLS r0,r1,#9
0000a2 f7fff7ff BL RCC_APB2PeriphClockCmd
;;;165 }
0000a6 bd10 POP {r4,pc}
;;;166
ENDP
main PROC
;;;46 int main(void)
;;;47 {
0000a8 b510 PUSH {r4,lr}
;;;48 #ifdef DEBUG
;;;49 debug();
;;;50 #endif
;;;51
;;;52 /* System Clocks Configuration ---------------------------------------------*/
;;;53 RCC_Configuration();
0000aa f7fff7ff BL RCC_Configuration
;;;54
;;;55 /* GPIO Configuration ------------------------------------------------------*/
;;;56 GPIO_Configuration();
0000ae f7fff7ff BL GPIO_Configuration
;;;57
;;;58 /* NVIC configuration ------------------------------------------------------*/
;;;59 NVIC_Configuration();
0000b2 f7fff7ff BL NVIC_Configuration
;;;60
;;;61 /* DMA Channel1 Configuration ----------------------------------------------*/
;;;62 DMA_DeInit(DMA_Channel1);
0000b6 4827 LDR r0,|L1.340|
0000b8 f7fff7ff BL DMA_DeInit
;;;63 DMA_InitStructure.DMA_PeripheralBaseAddr = ADC1_DR_Address;
0000bc 4826 LDR r0,|L1.344|
0000be 4927 LDR r1,|L1.348|
0000c0 6008 STR r0,[r1,#0] ; DMA_InitStructure
;;;64 DMA_InitStructure.DMA_MemoryBaseAddr = (u32)&ADC_ConvertedValue;
0000c2 4827 LDR r0,|L1.352|
0000c4 6048 STR r0,[r1,#4] ; DMA_InitStructure
;;;65 DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralSRC;
0000c6 2000 MOVS r0,#0
0000c8 6088 STR r0,[r1,#8] ; DMA_InitStructure
;;;66 DMA_InitStructure.DMA_BufferSize = 1;
0000ca 2001 MOVS r0,#1
0000cc 60c8 STR r0,[r1,#0xc] ; DMA_InitStructure
;;;67 DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
0000ce 2000 MOVS r0,#0
0000d0 6108 STR r0,[r1,#0x10] ; DMA_InitStructure
;;;68 DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Disable;
0000d2 6148 STR r0,[r1,#0x14] ; DMA_InitStructure
;;;69 DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_HalfWord;
0000d4 f44ff44f MOV r0,#0x100
0000d8 6188 STR r0,[r1,#0x18] ; DMA_InitStructure
;;;70 DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_HalfWord;
0000da 0080 LSLS r0,r0,#2
0000dc 61c8 STR r0,[r1,#0x1c] ; DMA_InitStructure
;;;71 DMA_InitStructure.DMA_Mode = DMA_Mode_Circular;
0000de 2020 MOVS r0,#0x20
0000e0 6208 STR r0,[r1,#0x20] ; DMA_InitStructure
;;;72 DMA_InitStructure.DMA_Priority = DMA_Priority_High;
0000e2 0200 LSLS r0,r0,#8
0000e4 6248 STR r0,[r1,#0x24] ; DMA_InitStructure
;;;73 DMA_InitStructure.DMA_M2M = DMA_M2M_Disable;
0000e6 2000 MOVS r0,#0
0000e8 6288 STR r0,[r1,#0x28] ; DMA_InitStructure
;;;74 DMA_Init(DMA_Channel1, &DMA_InitStructure);
0000ea 481a LDR r0,|L1.340|
0000ec f7fff7ff BL DMA_Init
;;;75
;;;76 /* Enable DMA Channel1 */
;;;77 DMA_Cmd(DMA_Channel1, ENABLE);
0000f0 2101 MOVS r1,#1
0000f2 4818 LDR r0,|L1.340|
0000f4 f7fff7ff BL DMA_Cmd
;;;78
;;;79
;;;80 /* ADCx Configuration (ADC1CLK = 14 MHz) -----------------------------------*/
;;;81 ADC_InitStructure.ADC_Mode = ADC_Mode_Independent;
0000f8 2000 MOVS r0,#0
0000fa 491a LDR r1,|L1.356|
0000fc 6008 STR r0,[r1,#0] ; ADC_InitStructure
;;;82 ADC_InitStructure.ADC_ScanConvMode = ENABLE;
0000fe 2001 MOVS r0,#1
000100 7108 STRB r0,[r1,#4] ; ADC_InitStructure
;;;83 ADC_InitStructure.ADC_ContinuousConvMode = ENABLE;
000102 7148 STRB r0,[r1,#5] ; ADC_InitStructure
;;;84 ADC_InitStructure.ADC_ExternalTrigConv = ADC_ExternalTrigConv_None;
000104 f44ff44f MOV r0,#0xe0000
000108 6088 STR r0,[r1,#8] ; ADC_InitStructure
;;;85 ADC_InitStructure.ADC_DataAlign = ADC_DataAlign_Right;
00010a 2000 MOVS r0,#0
00010c 60c8 STR r0,[r1,#0xc] ; ADC_InitStructure
;;;86 ADC_InitStructure.ADC_NbrOfChannel = 1;
00010e 2001 MOVS r0,#1
000110 7408 STRB r0,[r1,#0x10] ; ADC_InitStructure
;;;87 ADC_Init(ADC1, &ADC_InitStructure);
000112 4811 LDR r0,|L1.344|
000114 384c SUBS r0,r0,#0x4c
000116 f7fff7ff BL ADC_Init
;;;88
;;;89 /* ADCx Regular Channel14 Configuration */
;;;90 ADC_RegularChannelConfig(ADC1, ADC_Channel_14, 1, ADC_SampleTime_55Cycles5);
00011a 2305 MOVS r3,#5
00011c 2201 MOVS r2,#1
00011e 210e MOVS r1,#0xe
000120 480d LDR r0,|L1.344|
000122 384c SUBS r0,r0,#0x4c
000124 f7fff7ff BL ADC_RegularChannelConfig
;;;91
;;;92 /* Enable ADCx's DMA interface */
;;;93 ADC_DMACmd(ADC1, ENABLE);
000128 2101 MOVS r1,#1
00012a 480b LDR r0,|L1.344|
00012c 384c SUBS r0,r0,#0x4c
00012e f7fff7ff BL ADC_DMACmd
;;;94
;;;95 /* Enable ADCx */
;;;96 ADC_Cmd(ADC1, ENABLE);
000132 2101 MOVS r1,#1
000134 4808 LDR r0,|L1.344|
000136 384c SUBS r0,r0,#0x4c
000138 f7fff7ff BL ADC_Cmd
;;;97
;;;98 /* Start ADC1 Software Conversion */
;;;99 ADC_SoftwareStartConvCmd(ADC1, ENABLE);
00013c 2101 MOVS r1,#1
00013e 4806 LDR r0,|L1.344|
000140 384c SUBS r0,r0,#0x4c
000142 f7fff7ff BL ADC_SoftwareStartConvCmd
;;;100
;;;101 while(1)
000146 bf00 NOP
|L1.328|
000148 e7fe B |L1.328|
;;;102 {
;;;103 }
;;;104 }
;;;105
ENDP
00014a 0000 DCW 0x0000
|L1.332|
00014c 40011000 DCD 0x40011000
|L1.336|
000150 40022000 DCD 0x40022000
|L1.340|
000154 40020008 DCD 0x40020008
|L1.344|
000158 4001244c DCD 0x4001244c
|L1.348|
00015c 00000000 DCD DMA_InitStructure
|L1.352|
000160 00000000 DCD ADC_ConvertedValue
|L1.356|
000164 00000000 DCD ADC_InitStructure
AREA ||.data||, DATA, ALIGN=1
ADC_ConvertedValue
000000 0000 DCB 0x00,0x00
AREA ||.bss||, DATA, NOINIT, ALIGN=2
ADC_InitStructure
% 20
DMA_InitStructure
% 44
__ARM_use_no_argv EQU 0
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