stm32f10x_usart.txt

STM32 demo板的例程

; generated by ARM/Thumb C/C++ Compiler with , RVCT3.1 [Build 902] for uVision
; commandline ArmCC [--debug -c --asm --interleave -o..\obj\stm32f10x_usart.o --depend=..\obj\stm32f10x_usart.d --device=DARMSTM -I..\..\LAB2 -I..\..\library\src -IC:\Keil\ARM\INC\ST\STM32F10x -DVECT_TAB_RAM --omf_browse=..\obj\stm32f10x_usart.crf ..\..\library\src\stm32f10x_usart.c]
                          THUMB

                          AREA ||.text||, CODE, READONLY, ALIGN=2

                  USART_DeInit PROC
;;;92     void USART_DeInit(USART_TypeDef* USARTx)
;;;93     {
000000  b510              PUSH     {r4,lr}
000002  4604              MOV      r4,r0
;;;94       switch (*(u32*)&USARTx)
000004  48c5              LDR      r0,|L1.796|
000006  1820              ADDS     r0,r4,r0
000008  d00f              BEQ      |L1.42|
00000a  f5b0f5b0          CMP      r0,#0x400
00000e  d016              BEQ      |L1.62|
000010  f5b0f5b0          CMP      r0,#0xf400
000014  d11d              BNE      |L1.82|
;;;95       {
;;;96         case USART1_BASE:
;;;97           RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, ENABLE);
000016  2101              MOVS     r1,#1
000018  0388              LSLS     r0,r1,#14
00001a  f7fff7ff          BL       RCC_APB2PeriphResetCmd
;;;98           RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, DISABLE);
00001e  2100              MOVS     r1,#0
000020  f44ff44f          MOV      r0,#0x4000
000024  f7fff7ff          BL       RCC_APB2PeriphResetCmd
;;;99           break;
000028  e014              B        |L1.84|
                  |L1.42|
;;;100    
;;;101        case USART2_BASE:
;;;102          RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, ENABLE);
00002a  2101              MOVS     r1,#1
00002c  0448              LSLS     r0,r1,#17
00002e  f7fff7ff          BL       RCC_APB1PeriphResetCmd
;;;103          RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, DISABLE);
000032  2100              MOVS     r1,#0
000034  f44ff44f          MOV      r0,#0x20000
000038  f7fff7ff          BL       RCC_APB1PeriphResetCmd
;;;104          break;
00003c  e00a              B        |L1.84|
                  |L1.62|
;;;105    
;;;106        case USART3_BASE:
;;;107          RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, ENABLE);
00003e  2101              MOVS     r1,#1
000040  0488              LSLS     r0,r1,#18
000042  f7fff7ff          BL       RCC_APB1PeriphResetCmd
;;;108          RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, DISABLE);
000046  2100              MOVS     r1,#0
000048  f44ff44f          MOV      r0,#0x40000
00004c  f7fff7ff          BL       RCC_APB1PeriphResetCmd
;;;109          break;
000050  e000              B        |L1.84|
                  |L1.82|
;;;110    
;;;111        default:
;;;112          break;
000052  bf00              NOP      
                  |L1.84|
000054  bf00              NOP      
;;;113      }
;;;114    }
000056  bd10              POP      {r4,pc}
                          ENDP

                  USART_Init PROC
;;;127    void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct)
;;;128    {
000058  e92de92d          PUSH     {r4-r9,lr}
00005c  b085              SUB      sp,sp,#0x14
00005e  4604              MOV      r4,r0
000060  460d              MOV      r5,r1
;;;129      u32 tmpreg = 0x00, apbclock = 0x00;
000062  2600              MOVS     r6,#0
000064  2700              MOVS     r7,#0
;;;130      u32 integerdivider = 0x00;
000066  46b0              MOV      r8,r6
;;;131      u32 fractionaldivider = 0x00;
000068  46b1              MOV      r9,r6
;;;132      RCC_ClocksTypeDef RCC_ClocksStatus;
;;;133    
;;;134      /* Check the parameters */
;;;135      assert(IS_USART_BAUDRATE(USART_InitStruct->USART_BaudRate));  
;;;136      assert(IS_USART_WORD_LENGTH(USART_InitStruct->USART_WordLength));
;;;137      assert(IS_USART_STOPBITS(USART_InitStruct->USART_StopBits));
;;;138      assert(IS_USART_PARITY(USART_InitStruct->USART_Parity));
;;;139      assert(IS_USART_HARDWARE_FLOW_CONTROL(USART_InitStruct->USART_HardwareFlowControl));
;;;140      assert(IS_USART_MODE(USART_InitStruct->USART_Mode));
;;;141      assert(IS_USART_CLOCK(USART_InitStruct->USART_Clock));
;;;142      assert(IS_USART_CPOL(USART_InitStruct->USART_CPOL));
;;;143      assert(IS_USART_CPHA(USART_InitStruct->USART_CPHA));
;;;144      assert(IS_USART_LASTBIT(USART_InitStruct->USART_LastBit));              
;;;145      
;;;146    /*---------------------------- USART CR2 Configuration -----------------------*/
;;;147      tmpreg = USARTx->CR2;
00006a  8a26              LDRH     r6,[r4,#0x10]
;;;148      /* Clear STOP[13:12], CLKEN, CPOL, CPHA and LBCL bits */
;;;149      tmpreg &= CR2_CLEAR_Mask;
00006c  f24cf24c          MOV      r0,#0xc0ff
000070  4006              ANDS     r6,r6,r0
;;;150    
;;;151      /* Configure the USART Stop Bits, Clock, CPOL, CPHA and LastBit ------------*/
;;;152      /* Set STOP[13:12] bits according to USART_Mode value */
;;;153      /* Set CPOL bit according to USART_CPOL value */
;;;154      /* Set CPHA bit according to USART_CPHA value */
;;;155      /* Set LBCL bit according to USART_LastBit value */
;;;156      tmpreg |= (u32)USART_InitStruct->USART_StopBits | USART_InitStruct->USART_Clock |
000072  88e8              LDRH     r0,[r5,#6]
000074  89e9              LDRH     r1,[r5,#0xe]
000076  4308              ORRS     r0,r0,r1
000078  8a29              LDRH     r1,[r5,#0x10]
00007a  4308              ORRS     r0,r0,r1
00007c  8a69              LDRH     r1,[r5,#0x12]
00007e  4308              ORRS     r0,r0,r1
000080  8aa9              LDRH     r1,[r5,#0x14]
000082  4308              ORRS     r0,r0,r1
000084  4306              ORRS     r6,r6,r0
;;;157                USART_InitStruct->USART_CPOL | USART_InitStruct->USART_CPHA |
;;;158                USART_InitStruct->USART_LastBit;
;;;159    
;;;160      /* Write to USART CR2 */
;;;161      USARTx->CR2 = (u16)tmpreg;
000086  8226              STRH     r6,[r4,#0x10]
;;;162    
;;;163    /*---------------------------- USART CR1 Configuration -----------------------*/
;;;164      tmpreg = 0x00;
000088  2600              MOVS     r6,#0
;;;165      tmpreg = USARTx->CR1;
00008a  89a6              LDRH     r6,[r4,#0xc]
;;;166      /* Clear M, PCE, PS, TE and RE bits */
;;;167      tmpreg &= CR1_CLEAR_Mask;
00008c  f64ef64e          MOV      r0,#0xe9f3
000090  4006              ANDS     r6,r6,r0
;;;168    
;;;169      /* Configure the USART Word Length, Parity and mode ----------------------- */
;;;170      /* Set the M bits according to USART_WordLength value */
;;;171      /* Set PCE and PS bits according to USART_Parity value */
;;;172      /* Set TE and RE bits according to USART_Mode value */
;;;173      tmpreg |= (u32)USART_InitStruct->USART_WordLength | USART_InitStruct->USART_Parity |
000092  88a8              LDRH     r0,[r5,#4]
000094  8929              LDRH     r1,[r5,#8]
000096  4308              ORRS     r0,r0,r1
000098  89a9              LDRH     r1,[r5,#0xc]
00009a  4308              ORRS     r0,r0,r1
00009c  4306              ORRS     r6,r6,r0
;;;174                USART_InitStruct->USART_Mode;
;;;175    
;;;176      /* Write to USART CR1 */
;;;177      USARTx->CR1 = (u16)tmpreg;
00009e  81a6              STRH     r6,[r4,#0xc]
;;;178    
;;;179    /*---------------------------- USART CR3 Configuration -----------------------*/
;;;180      tmpreg = 0x00;
0000a0  2600              MOVS     r6,#0
;;;181      tmpreg = USARTx->CR3;
0000a2  8aa6              LDRH     r6,[r4,#0x14]
;;;182      /* Clear CTSE and RTSE bits */
;;;183      tmpreg &= CR3_CLEAR_Mask;
0000a4  f64ff64f          MOV      r0,#0xfcff
0000a8  4006              ANDS     r6,r6,r0
;;;184    
;;;185      /* Configure the USART HFC -------------------------------------------------*/
;;;186      /* Set CTSE and RTSE bits according to USART_HardwareFlowControl value */
;;;187      tmpreg |= USART_InitStruct->USART_HardwareFlowControl;
0000aa  8968              LDRH     r0,[r5,#0xa]
0000ac  4306              ORRS     r6,r6,r0
;;;188    
;;;189      /* Write to USART CR3 */
;;;190      USARTx->CR3 = (u16)tmpreg;
0000ae  82a6              STRH     r6,[r4,#0x14]
;;;191    
;;;192    /*---------------------------- USART BRR Configuration -----------------------*/
;;;193      tmpreg = 0x00;
0000b0  2600              MOVS     r6,#0
;;;194    
;;;195      /* Configure the USART Baud Rate -------------------------------------------*/
;;;196      RCC_GetClocksFreq(&RCC_ClocksStatus);
0000b2  4668              MOV      r0,sp
0000b4  f7fff7ff          BL       RCC_GetClocksFreq
;;;197      if ((*(u32*)&USARTx) == USART1_BASE)
0000b8  4899              LDR      r0,|L1.800|
0000ba  4284              CMP      r4,r0
0000bc  d101              BNE      |L1.194|
;;;198      {
;;;199        apbclock = RCC_ClocksStatus.PCLK2_Frequency;
0000be  9f03              LDR      r7,[sp,#0xc]
0000c0  e000              B        |L1.196|
                  |L1.194|
;;;200      }
;;;201      else
;;;202      {
;;;203        apbclock = RCC_ClocksStatus.PCLK1_Frequency;
0000c2  9f02              LDR      r7,[sp,#8]
                  |L1.196|
;;;204      }
;;;205    
;;;206      /* Determine the integer part */
;;;207      integerdivider = ((0x19 * apbclock) / (0x04 * (USART_InitStruct->USART_BaudRate)));
0000c4  2019              MOVS     r0,#0x19
0000c6  4378              MULS     r0,r7,r0
0000c8  6829              LDR      r1,[r5,#0]
0000ca  0089              LSLS     r1,r1,#2
0000cc  fbb0fbb0          UDIV     r8,r0,r1
;;;208      tmpreg = (integerdivider / 0x64) << 0x04;
0000d0  2064              MOVS     r0,#0x64
0000d2  fbb8fbb8          UDIV     r0,r8,r0
0000d6  0106              LSLS     r6,r0,#4
;;;209    
;;;210      /* Determine the fractional part */
;;;211      fractionaldivider = integerdivider - (0x64 * (tmpreg >> 0x04));
0000d8  0930              LSRS     r0,r6,#4
0000da  2164              MOVS     r1,#0x64
0000dc  fb01fb01          MLS      r9,r1,r0,r8
;;;212      tmpreg |= ((((fractionaldivider * 0x10) + 0x32) / 0x64)) & ((u8)0x0F);
0000e0  2132              MOVS     r1,#0x32
0000e2  eb01eb01          ADD      r0,r1,r9,LSL #4
0000e6  2164              MOVS     r1,#0x64
0000e8  fbb0fbb0          UDIV     r0,r0,r1
0000ec  f000f000          AND      r0,r0,#0xf
0000f0  4306              ORRS     r6,r6,r0
;;;213    
;;;214      /* Write to USART BRR */
;;;215      USARTx->BRR = (u16)tmpreg;
0000f2  8126              STRH     r6,[r4,#8]
;;;216    }
0000f4  b005              ADD      sp,sp,#0x14
0000f6  e8bde8bd          POP      {r4-r9,pc}
                          ENDP

                  USART_StructInit PROC
;;;228      /* USART_InitStruct members default value */
;;;229      USART_InitStruct->USART_BaudRate = 0x2580; /* 9600 Baud */
0000fa  f44ff44f          MOV      r1,#0x2580
0000fe  6001              STR      r1,[r0,#0]
;;;230      USART_InitStruct->USART_WordLength = USART_WordLength_8b;
000100  2100              MOVS     r1,#0
000102  8081              STRH     r1,[r0,#4]
;;;231      USART_InitStruct->USART_StopBits = USART_StopBits_1;
000104  80c1              STRH     r1,[r0,#6]
;;;232      USART_InitStruct->USART_Parity = USART_Parity_No ;
000106  8101              STRH     r1,[r0,#8]
;;;233      USART_InitStruct->USART_HardwareFlowControl = USART_HardwareFlowControl_None;
000108  8141              STRH     r1,[r0,#0xa]
;;;234      USART_InitStruct->USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
00010a  210c              MOVS     r1,#0xc
00010c  8181              STRH     r1,[r0,#0xc]
;;;235      USART_InitStruct->USART_Clock = USART_Clock_Disable;
00010e  2100              MOVS     r1,#0
000110  81c1              STRH     r1,[r0,#0xe]
;;;236      USART_InitStruct->USART_CPOL = USART_CPOL_Low;
000112  8201              STRH     r1,[r0,#0x10]
;;;237      USART_InitStruct->USART_CPHA = USART_CPHA_1Edge;
000114  8241              STRH     r1,[r0,#0x12]
;;;238      USART_InitStruct->USART_LastBit = USART_LastBit_Disable;
000116  8281              STRH     r1,[r0,#0x14]
;;;239    }
000118  4770              BX       lr
                          ENDP

                  USART_Cmd PROC
;;;255      
;;;256      if (NewState != DISABLE)
00011a  b121              CBZ      r1,|L1.294|
;;;257      {
;;;258        /* Enable the selected USART by setting the RUN bit in the CR1 register */
;;;259        USARTx->CR1 |= CR1_RUN_Set;
00011c  8982              LDRH     r2,[r0,#0xc]
00011e  f442f442          ORR      r2,r2,#0x2000
000122  8182              STRH     r2,[r0,#0xc]
000124  e004              B        |L1.304|
                  |L1.294|
;;;260      }
;;;261      else
;;;262      {
;;;263        /* Disable the selected USART by clearing the RUN bit in the CR1 register */
;;;264        USARTx->CR1 &= CR1_RUN_Reset;
000126  8982              LDRH     r2,[r0,#0xc]
000128  f64df64d          MOV      r3,#0xdfff