📄 stm32f10x_rcc.txt
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;;;734
;;;735 /* Get PCLK1 prescaler */
;;;736 tmp = RCC->CFGR & CFGR_PPRE1_Set_Mask;
0001f4 6041 STR r1,[r0,#4]
0001f6 6853 LDR r3,[r2,#4]
0001f8 f403f403 AND r3,r3,#0x700
;;;737 tmp = tmp >> 8;
0001fc 0a1b LSRS r3,r3,#8
;;;738 presc = APBAHBPrescTable[tmp];
0001fe f81cf81c LDRB r3,[r12,r3]
;;;739
;;;740 /* PCLK1 clock frequency */
;;;741 RCC_Clocks->PCLK1_Frequency = RCC_Clocks->HCLK_Frequency >> presc;
000202 fa21fa21 LSR r3,r1,r3
;;;742
;;;743 /* Get PCLK2 prescaler */
;;;744 tmp = RCC->CFGR & CFGR_PPRE2_Set_Mask;
000206 6083 STR r3,[r0,#8]
000208 6853 LDR r3,[r2,#4]
00020a f403f403 AND r3,r3,#0x3800
;;;745 tmp = tmp >> 11;
00020e 0adb LSRS r3,r3,#11
;;;746 presc = APBAHBPrescTable[tmp];
000210 f81cf81c LDRB r3,[r12,r3]
;;;747
;;;748 /* PCLK2 clock frequency */
;;;749 RCC_Clocks->PCLK2_Frequency = RCC_Clocks->HCLK_Frequency >> presc;
000214 40d9 LSRS r1,r1,r3
;;;750
;;;751 /* Get ADCCLK prescaler */
;;;752 tmp = RCC->CFGR & CFGR_ADCPRE_Set_Mask;
000216 60c1 STR r1,[r0,#0xc]
000218 6852 LDR r2,[r2,#4]
;;;753 tmp = tmp >> 14;
;;;754 presc = ADCPrescTable[tmp];
00021a f1acf1ac SUB r3,r12,#4
00021e f402f402 AND r2,r2,#0xc000
000222 0b92 LSRS r2,r2,#14
000224 5c9a LDRB r2,[r3,r2]
;;;755
;;;756 /* ADCCLK clock frequency */
;;;757 RCC_Clocks->ADCCLK_Frequency = RCC_Clocks->PCLK2_Frequency / presc;
000226 fbb1fbb1 UDIV r1,r1,r2
;;;758 }
00022a 6101 STR r1,[r0,#0x10]
00022c bc10 POP {r4}
00022e 4770 BX lr
ENDP
RCC_AHBPeriphClockCmd PROC
;;;774 void RCC_AHBPeriphClockCmd(u32 RCC_AHBPeriph, FunctionalState NewState)
;;;775 {
000230 4a23 LDR r2,|L1.704|
;;;776 /* Check the parameters */
;;;777 assert(IS_RCC_AHB_PERIPH(RCC_AHBPeriph));
;;;778 assert(IS_FUNCTIONAL_STATE(NewState));
;;;779
;;;780 if (NewState != DISABLE)
000232 2900 CMP r1,#0
;;;781 {
;;;782 RCC->AHBENR |= RCC_AHBPeriph;
000234 6951 LDR r1,[r2,#0x14]
;;;783 }
;;;784 else
;;;785 {
;;;786 RCC->AHBENR &= ~RCC_AHBPeriph;
000236 bf0c ITE EQ
000238 ea21ea21 BICEQ r0,r1,r0
00023c 4308 ORRNE r0,r0,r1
00023e 6150 STR r0,[r2,#0x14]
;;;787 }
;;;788 }
000240 4770 BX lr
ENDP
RCC_APB2PeriphClockCmd PROC
;;;805 void RCC_APB2PeriphClockCmd(u32 RCC_APB2Periph, FunctionalState NewState)
;;;806 {
000242 4a1f LDR r2,|L1.704|
;;;807 /* Check the parameters */
;;;808 assert(IS_RCC_APB2_PERIPH(RCC_APB2Periph));
;;;809 assert(IS_FUNCTIONAL_STATE(NewState));
;;;810
;;;811 if (NewState != DISABLE)
000244 2900 CMP r1,#0
;;;812 {
;;;813 RCC->APB2ENR |= RCC_APB2Periph;
000246 6991 LDR r1,[r2,#0x18]
;;;814 }
;;;815 else
;;;816 {
;;;817 RCC->APB2ENR &= ~RCC_APB2Periph;
000248 bf0c ITE EQ
00024a ea21ea21 BICEQ r0,r1,r0
00024e 4308 ORRNE r0,r0,r1
000250 6190 STR r0,[r2,#0x18]
;;;818 }
;;;819 }
000252 4770 BX lr
ENDP
RCC_APB1PeriphClockCmd PROC
;;;837 void RCC_APB1PeriphClockCmd(u32 RCC_APB1Periph, FunctionalState NewState)
;;;838 {
000254 4a1a LDR r2,|L1.704|
;;;839 /* Check the parameters */
;;;840 assert(IS_RCC_APB1_PERIPH(RCC_APB1Periph));
;;;841 assert(IS_FUNCTIONAL_STATE(NewState));
;;;842
;;;843 if (NewState != DISABLE)
000256 2900 CMP r1,#0
;;;844 {
;;;845 RCC->APB1ENR |= RCC_APB1Periph;
000258 69d1 LDR r1,[r2,#0x1c]
;;;846 }
;;;847 else
;;;848 {
;;;849 RCC->APB1ENR &= ~RCC_APB1Periph;
00025a bf0c ITE EQ
00025c ea21ea21 BICEQ r0,r1,r0
000260 4308 ORRNE r0,r0,r1
000262 61d0 STR r0,[r2,#0x1c]
;;;850 }
;;;851 }
000264 4770 BX lr
ENDP
RCC_APB2PeriphResetCmd PROC
;;;867 void RCC_APB2PeriphResetCmd(u32 RCC_APB2Periph, FunctionalState NewState)
;;;868 {
000266 4a16 LDR r2,|L1.704|
;;;869 /* Check the parameters */
;;;870 assert(IS_RCC_APB2_PERIPH(RCC_APB2Periph));
;;;871 assert(IS_FUNCTIONAL_STATE(NewState));
;;;872
;;;873 if (NewState != DISABLE)
000268 2900 CMP r1,#0
;;;874 {
;;;875 RCC->APB2RSTR |= RCC_APB2Periph;
00026a 68d1 LDR r1,[r2,#0xc]
;;;876 }
;;;877 else
;;;878 {
;;;879 RCC->APB2RSTR &= ~RCC_APB2Periph;
00026c bf0c ITE EQ
00026e ea21ea21 BICEQ r0,r1,r0
000272 4308 ORRNE r0,r0,r1
000274 60d0 STR r0,[r2,#0xc]
;;;880 }
;;;881 }
000276 4770 BX lr
ENDP
RCC_APB1PeriphResetCmd PROC
;;;898 void RCC_APB1PeriphResetCmd(u32 RCC_APB1Periph, FunctionalState NewState)
;;;899 {
000278 4a11 LDR r2,|L1.704|
;;;900 /* Check the parameters */
;;;901 assert(IS_RCC_APB1_PERIPH(RCC_APB1Periph));
;;;902 assert(IS_FUNCTIONAL_STATE(NewState));
;;;903
;;;904 if (NewState != DISABLE)
00027a 2900 CMP r1,#0
;;;905 {
;;;906 RCC->APB1RSTR |= RCC_APB1Periph;
00027c 6911 LDR r1,[r2,#0x10]
;;;907 }
;;;908 else
;;;909 {
;;;910 RCC->APB1RSTR &= ~RCC_APB1Periph;
00027e bf0c ITE EQ
000280 ea21ea21 BICEQ r0,r1,r0
000284 4308 ORRNE r0,r0,r1
000286 6110 STR r0,[r2,#0x10]
;;;911 }
;;;912 }
000288 4770 BX lr
ENDP
RCC_BackupResetCmd PROC
;;;922 void RCC_BackupResetCmd(FunctionalState NewState)
;;;923 {
00028a 4916 LDR r1,|L1.740|
;;;924 /* Check the parameters */
;;;925 assert(IS_FUNCTIONAL_STATE(NewState));
;;;926
;;;927 *(vu32 *) BDCR_BDRST_BB = (u32)NewState;
00028c 6008 STR r0,[r1,#0]
;;;928 }
00028e 4770 BX lr
ENDP
RCC_ClockSecuritySystemCmd PROC
;;;942
;;;943 *(vu32 *) CR_CSSON_BB = (u32)NewState;
000290 490d LDR r1,|L1.712|
000292 64c8 STR r0,[r1,#0x4c]
;;;944 }
000294 4770 BX lr
ENDP
RCC_MCOConfig PROC
;;;964 /* Perform Byte access to MCO[26:24] bits to select the MCO source */
;;;965 *(vu8 *) 0x40021007 = RCC_MCO;
000296 490a LDR r1,|L1.704|
000298 71c8 STRB r0,[r1,#7]
;;;966 }
00029a 4770 BX lr
ENDP
RCC_ClearFlag PROC
;;;1040 /* Set RMVF bit to clear the reset flags */
;;;1041 RCC->CSR |= CSR_RMVF_Set;
00029c 4808 LDR r0,|L1.704|
00029e 6a41 LDR r1,[r0,#0x24]
0002a0 f041f041 ORR r1,r1,#0x1000000
0002a4 6241 STR r1,[r0,#0x24]
;;;1042 }
0002a6 4770 BX lr
ENDP
RCC_GetITStatus PROC
;;;1065 /* Check the status of the specified RCC interrupt */
;;;1066 if ((RCC->CIR & RCC_IT) != (u32)RESET)
0002a8 4a05 LDR r2,|L1.704|
0002aa 4601 MOV r1,r0
0002ac 6892 LDR r2,[r2,#8]
0002ae 2000 MOVS r0,#0
0002b0 420a TST r2,r1
;;;1067 {
;;;1068 bitstatus = SET;
0002b2 bf18 IT NE
0002b4 2001 MOVNE r0,#1
;;;1069 }
;;;1070 else
;;;1071 {
;;;1072 bitstatus = RESET;
;;;1073 }
;;;1074
;;;1075 /* Return the RCC_IT status */
;;;1076 return bitstatus;
;;;1077 }
0002b6 4770 BX lr
ENDP
RCC_ClearITPendingBit PROC
;;;1099 pending bits */
;;;1100 *(vu8 *) 0x4002100A = RCC_IT;
0002b8 4901 LDR r1,|L1.704|
0002ba 7288 STRB r0,[r1,#0xa]
;;;1101 }
0002bc 4770 BX lr
ENDP
0002be 0000 DCW 0x0000
|L1.704|
0002c0 40021000 DCD 0x40021000
|L1.708|
0002c4 f8ff0000 DCD 0xf8ff0000
|L1.712|
0002c8 42420000 DCD 0x42420000
|L1.716|
0002cc 424200d8 DCD 0x424200d8
|L1.720|
0002d0 42420480 DCD 0x42420480
|L1.724|
0002d4 4242043c DCD 0x4242043c
|L1.728|
0002d8 007a1200 DCD 0x007a1200
|L1.732|
0002dc 003d0900 DCD 0x003d0900
|L1.736|
0002e0 00000004 DCD ||.constdata||+0x4
|L1.740|
0002e4 42420440 DCD 0x42420440
AREA ||.constdata||, DATA, READONLY, ALIGN=0
ADCPrescTable
000000 02040608 DCB 0x02,0x04,0x06,0x08
APBAHBPrescTable
000004 00000000 DCB 0x00,0x00,0x00,0x00
000008 01020304 DCB 0x01,0x02,0x03,0x04
00000c 01020304 DCB 0x01,0x02,0x03,0x04
000010 06070809 DCB 0x06,0x07,0x08,0x09
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