📄 stm32f10x_rcc.txt
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;;;411 tmpreg |= RCC_HCLK;
000116 4308 ORRS r0,r0,r1
;;;412
;;;413 /* Store the new value */
;;;414 RCC->CFGR = tmpreg;
000118 6050 STR r0,[r2,#4]
;;;415 }
00011a 4770 BX lr
ENDP
RCC_PCLK1Config PROC
;;;437
;;;438 tmpreg = RCC->CFGR;
00011c 4a68 LDR r2,|L1.704|
00011e 6851 LDR r1,[r2,#4]
;;;439
;;;440 /* Clear PPRE1[10:8] bits */
;;;441 tmpreg &= CFGR_PPRE1_Reset_Mask;
000120 f421f421 BIC r1,r1,#0x700
;;;442
;;;443 /* Set PPRE1[10:8] bits according to RCC_PCLK1 value */
;;;444 tmpreg |= RCC_PCLK1;
000124 4308 ORRS r0,r0,r1
;;;445
;;;446 /* Store the new value */
;;;447 RCC->CFGR = tmpreg;
000126 6050 STR r0,[r2,#4]
;;;448 }
000128 4770 BX lr
ENDP
RCC_PCLK2Config PROC
;;;470
;;;471 tmpreg = RCC->CFGR;
00012a 4a65 LDR r2,|L1.704|
00012c 6851 LDR r1,[r2,#4]
;;;472
;;;473 /* Clear PPRE2[13:11] bits */
;;;474 tmpreg &= CFGR_PPRE2_Reset_Mask;
00012e f421f421 BIC r1,r1,#0x3800
;;;475
;;;476 /* Set PPRE2[13:11] bits according to RCC_PCLK2 value */
;;;477 tmpreg |= RCC_PCLK2 << 3;
000132 ea41ea41 ORR r0,r1,r0,LSL #3
;;;478
;;;479 /* Store the new value */
;;;480 RCC->CFGR = tmpreg;
000136 6050 STR r0,[r2,#4]
;;;481 }
000138 4770 BX lr
ENDP
RCC_ITConfig PROC
;;;499 void RCC_ITConfig(u8 RCC_IT, FunctionalState NewState)
;;;500 {
00013a 4a61 LDR r2,|L1.704|
;;;501 /* Check the parameters */
;;;502 assert(IS_RCC_IT(RCC_IT));
;;;503 assert(IS_FUNCTIONAL_STATE(NewState));
;;;504
;;;505 if (NewState != DISABLE)
00013c 2900 CMP r1,#0
;;;506 {
;;;507 /* Perform Byte access to RCC_CIR[12:8] bits to enable the selected interrupts */
;;;508 *(vu8 *) 0x40021009 |= RCC_IT;
00013e 7a51 LDRB r1,[r2,#9]
;;;509 }
;;;510 else
;;;511 {
;;;512 /* Perform Byte access to RCC_CIR[12:8] bits to disable the selected interrupts */
;;;513 *(vu8 *) 0x40021009 &= ~(u32)RCC_IT;
000140 bf0c ITE EQ
000142 ea21ea21 BICEQ r0,r1,r0
000146 4308 ORRNE r0,r0,r1
000148 7250 STRB r0,[r2,#9]
;;;514 }
;;;515 }
00014a 4770 BX lr
ENDP
RCC_USBCLKConfig PROC
;;;530 void RCC_USBCLKConfig(u32 RCC_USBCLKSource)
;;;531 {
00014c 495f LDR r1,|L1.716|
;;;532 /* Check the parameters */
;;;533 assert(IS_RCC_USBCLK_SOURCE(RCC_USBCLKSource));
;;;534
;;;535 *(vu32 *) CFGR_USBPRE_BB = RCC_USBCLKSource;
00014e 6008 STR r0,[r1,#0]
;;;536 }
000150 4770 BX lr
ENDP
RCC_ADCCLKConfig PROC
;;;557
;;;558 tmpreg = RCC->CFGR;
000152 4a5b LDR r2,|L1.704|
000154 6851 LDR r1,[r2,#4]
;;;559
;;;560 /* Clear ADCPRE[15:14] bits */
;;;561 tmpreg &= CFGR_ADCPRE_Reset_Mask;
000156 f421f421 BIC r1,r1,#0xc000
;;;562
;;;563 /* Set ADCPRE[15:14] bits according to RCC_ADCCLK value */
;;;564 tmpreg |= RCC_ADCCLK;
00015a 4308 ORRS r0,r0,r1
;;;565
;;;566 /* Store the new value */
;;;567 RCC->CFGR = tmpreg;
00015c 6050 STR r0,[r2,#4]
;;;568 }
00015e 4770 BX lr
ENDP
RCC_LSEConfig PROC
;;;588 /* Reset LSEON bit */
;;;589 *(vu8 *) BDCR_BASE = RCC_LSE_OFF;
000160 4957 LDR r1,|L1.704|
000162 2200 MOVS r2,#0
000164 f881f881 STRB r2,[r1,#0x20]
;;;590
;;;591 /* Reset LSEBYP bit */
;;;592 *(vu8 *) BDCR_BASE = RCC_LSE_OFF;
000168 f881f881 STRB r2,[r1,#0x20]
;;;593
;;;594 /* Configure LSE (RCC_LSE_OFF is already covered by the code section above) */
;;;595 switch(RCC_LSE)
00016c 2801 CMP r0,#1
00016e d003 BEQ |L1.376|
000170 2804 CMP r0,#4
;;;596 {
;;;597 case RCC_LSE_ON:
;;;598 /* Set LSEON bit */
;;;599 *(vu8 *) BDCR_BASE = RCC_LSE_ON;
;;;600 break;
;;;601
;;;602 case RCC_LSE_Bypass:
;;;603 /* Set LSEBYP and LSEON bits */
;;;604 *(vu8 *) BDCR_BASE = RCC_LSE_Bypass | RCC_LSE_ON;
;;;605 break;
;;;606
;;;607 default:
;;;608 break;
;;;609 }
;;;610 }
000172 bf18 IT NE
000174 4770 BXNE lr
000176 2005 MOVS r0,#5
|L1.376|
000178 f881f881 STRB r0,[r1,#0x20]
00017c 4770 BX lr
ENDP
RCC_LSICmd PROC
;;;621 void RCC_LSICmd(FunctionalState NewState)
;;;622 {
00017e 4954 LDR r1,|L1.720|
;;;623 /* Check the parameters */
;;;624 assert(IS_FUNCTIONAL_STATE(NewState));
;;;625
;;;626 *(vu32 *) CSR_LSION_BB = (u32)NewState;
000180 6008 STR r0,[r1,#0]
;;;627 }
000182 4770 BX lr
ENDP
RCC_RTCCLKConfig PROC
;;;648 /* Select the RTC clock source */
;;;649 RCC->BDCR |= RCC_RTCCLKSource;
000184 494e LDR r1,|L1.704|
000186 6a0a LDR r2,[r1,#0x20]
000188 4310 ORRS r0,r0,r2
00018a 6208 STR r0,[r1,#0x20]
;;;650 }
00018c 4770 BX lr
ENDP
RCC_RTCCLKCmd PROC
;;;662 void RCC_RTCCLKCmd(FunctionalState NewState)
;;;663 {
00018e 4951 LDR r1,|L1.724|
;;;664 /* Check the parameters */
;;;665 assert(IS_FUNCTIONAL_STATE(NewState));
;;;666
;;;667 *(vu32 *) BDCR_RTCEN_BB = (u32)NewState;
000190 6008 STR r0,[r1,#0]
;;;668 }
000192 4770 BX lr
ENDP
RCC_GetClocksFreq PROC
;;;678 void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks)
;;;679 {
000194 b410 PUSH {r4}
;;;680 u32 tmp = 0, pllmull = 0, pllsource = 0, presc = 0;
;;;681
;;;682 /* Get SYSCLK source -------------------------------------------------------*/
;;;683 tmp = RCC->CFGR & CFGR_SWS_Mask;
000196 4a4a LDR r2,|L1.704|
000198 6851 LDR r1,[r2,#4]
00019a 4b4f LDR r3,|L1.728|
00019c f011f011 ANDS r1,r1,#0xc
;;;684
;;;685 switch (tmp)
0001a0 bf18 IT NE
0001a2 2904 CMPNE r1,#4
0001a4 d001 BEQ |L1.426|
0001a6 2908 CMP r1,#8
0001a8 d001 BEQ |L1.430|
|L1.426|
;;;686 {
;;;687 case 0x00: /* HSI used as system clock */
;;;688 RCC_Clocks->SYSCLK_Frequency = HSI_Value;
0001aa 6003 STR r3,[r0,#0]
0001ac e017 B |L1.478|
|L1.430|
;;;689 break;
;;;690
;;;691 case 0x04: /* HSE used as system clock */
;;;692 RCC_Clocks->SYSCLK_Frequency = HSE_Value;
;;;693 break;
;;;694
;;;695 case 0x08: /* PLL used as system clock */
;;;696 /* Get PLL clock source and multiplication factor ----------------------*/
;;;697 pllmull = RCC->CFGR & CFGR_PLLMull_Mask;
0001ae 6851 LDR r1,[r2,#4]
;;;698 pllmull = ( pllmull >> 18) + 2;
0001b0 f04ff04f MOV r12,#2
0001b4 f401f401 AND r1,r1,#0x3c0000
0001b8 eb0ceb0c ADD r1,r12,r1,LSR #18
;;;699
;;;700 pllsource = RCC->CFGR & CFGR_PLLSRC_Mask;
0001bc f8d2f8d2 LDR r12,[r2,#4]
0001c0 4c46 LDR r4,|L1.732|
0001c2 f41cf41c TST r12,#0x10000
;;;701
;;;702 if (pllsource == 0x00)
;;;703 {/* HSI oscillator clock divided by 2 selected as PLL clock entry */
;;;704 RCC_Clocks->SYSCLK_Frequency = (HSI_Value >> 1) * pllmull;
0001c6 bf04 ITT EQ
0001c8 4361 MULEQ r1,r4,r1
0001ca 6001 STREQ r1,[r0,#0]
0001cc d007 BEQ |L1.478|
;;;705 }
;;;706 else
;;;707 {/* HSE selected as PLL clock entry */
;;;708
;;;709 if ((RCC->CFGR & CFGR_PLLXTPRE_Mask) != (u32)RESET)
0001ce f8d2f8d2 LDR r12,[r2,#4]
0001d2 f41cf41c TST r12,#0x20000
;;;710 {/* HSE oscillator clock divided by 2 */
;;;711
;;;712 RCC_Clocks->SYSCLK_Frequency = (HSE_Value >> 1) * pllmull;
;;;713 }
;;;714 else
;;;715 {
;;;716 RCC_Clocks->SYSCLK_Frequency = HSE_Value * pllmull;
0001d6 bf0c ITE EQ
0001d8 4359 MULEQ r1,r3,r1
0001da 4361 MULNE r1,r4,r1
0001dc 6001 STR r1,[r0,#0]
|L1.478|
;;;717 }
;;;718 }
;;;719 break;
;;;720
;;;721 default:
;;;722 RCC_Clocks->SYSCLK_Frequency = HSI_Value;
;;;723 break;
;;;724 }
;;;725
;;;726 /* Compute HCLK, PCLK1, PCLK2 and ADCCLK clocks frequencies ----------------*/
;;;727 /* Get HCLK prescaler */
;;;728 tmp = RCC->CFGR & CFGR_HPRE_Set_Mask;
0001de 6851 LDR r1,[r2,#4]
;;;729 tmp = tmp >> 4;
;;;730 presc = APBAHBPrescTable[tmp];
0001e0 f8dff8df LDR r12,|L1.736|
0001e4 f001f001 AND r1,r1,#0xf0
0001e8 0909 LSRS r1,r1,#4
0001ea f81cf81c LDRB r1,[r12,r1]
;;;731
;;;732 /* HCLK clock frequency */
;;;733 RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc;
0001ee 6803 LDR r3,[r0,#0]
0001f0 fa23fa23 LSR r1,r3,r1
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