📄 stm32f10x_rcc.txt
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; generated by ARM/Thumb C/C++ Compiler with Crescent Bay VAST 10.7u+w+:x ARM NEON, RVCT3.1 [Build 903] for uVision
; commandline ArmCC [--debug -c --asm --interleave -o..\obj\stm32f10x_rcc.o --depend=..\obj\stm32f10x_rcc.d --device=DARMSTM -O3 -Otime -I..\..\LAB6 -I..\..\library\inc -IC:\Keil\ARM\INC\ST\STM32F10x -DVECT_TAB_FLASH --omf_browse=..\obj\stm32f10x_rcc.crf ..\..\library\src\stm32f10x_rcc.c]
THUMB
AREA ||.text||, CODE, READONLY, ALIGN=2
RCC_DeInit PROC
;;;126 /* Disable APB2 Peripheral Reset */
;;;127 RCC->APB2RSTR = 0x00000000;
000000 48af LDR r0,|L1.704|
000002 2100 MOVS r1,#0
000004 60c1 STR r1,[r0,#0xc]
;;;128
;;;129 /* Disable APB1 Peripheral Reset */
;;;130 RCC->APB1RSTR = 0x00000000;
000006 6101 STR r1,[r0,#0x10]
;;;131
;;;132 /* FLITF and SRAM Clock ON */
;;;133 RCC->AHBENR = 0x00000014;
000008 2214 MOVS r2,#0x14
00000a 6142 STR r2,[r0,#0x14]
;;;134
;;;135 /* Disable APB2 Peripheral Clock */
;;;136 RCC->APB2ENR = 0x00000000;
00000c 6181 STR r1,[r0,#0x18]
;;;137
;;;138 /* Disable APB1 Peripheral Clock */
;;;139 RCC->APB1ENR = 0x00000000;
00000e 61c1 STR r1,[r0,#0x1c]
;;;140
;;;141 /* Set HSION bit */
;;;142 RCC->CR |= (u32)0x00000001;
000010 6802 LDR r2,[r0,#0]
000012 f042f042 ORR r2,r2,#1
000016 6002 STR r2,[r0,#0]
;;;143
;;;144 /* Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], ADCPRE[1:0] and MCO[2:0] bits*/
;;;145 RCC->CFGR &= 0xF8FF0000;
000018 6842 LDR r2,[r0,#4]
00001a 4baa LDR r3,|L1.708|
00001c 401a ANDS r2,r2,r3
00001e 6042 STR r2,[r0,#4]
;;;146
;;;147 /* Reset HSEON, CSSON and PLLON bits */
;;;148 RCC->CR &= 0xFEF6FFFF;
000020 6802 LDR r2,[r0,#0]
000022 f422f422 BIC r2,r2,#0x90000
000026 f022f022 BIC r2,r2,#0x1000000
00002a 6002 STR r2,[r0,#0]
;;;149
;;;150 /* Reset HSEBYP bit */
;;;151 RCC->CR &= 0xFFFBFFFF;
00002c 6802 LDR r2,[r0,#0]
00002e f422f422 BIC r2,r2,#0x40000
000032 6002 STR r2,[r0,#0]
;;;152
;;;153 /* Reset PLLSRC, PLLXTPRE, PLLMUL[3:0] and USBPRE bits */
;;;154 RCC->CFGR &= 0xFF80FFFF;
000034 6842 LDR r2,[r0,#4]
000036 f422f422 BIC r2,r2,#0x7f0000
00003a 6042 STR r2,[r0,#4]
;;;155
;;;156 /* Disable all interrupts */
;;;157 RCC->CIR = 0x00000000;
00003c 6081 STR r1,[r0,#8]
;;;158 }
00003e 4770 BX lr
ENDP
RCC_HSEConfig PROC
;;;180 /* Reset HSEON bit */
;;;181 RCC->CR &= CR_HSEON_Reset;
000040 499f LDR r1,|L1.704|
000042 680a LDR r2,[r1,#0]
000044 f422f422 BIC r2,r2,#0x10000
000048 600a STR r2,[r1,#0]
;;;182
;;;183 /* Reset HSEBYP bit */
;;;184 RCC->CR &= CR_HSEBYP_Reset;
00004a 680a LDR r2,[r1,#0]
;;;185
;;;186 /* Configure HSE (RCC_HSE_OFF is already covered by the code section above) */
;;;187 switch(RCC_HSE)
00004c f5b0f5b0 CMP r0,#0x10000
000050 f422f422 BIC r2,r2,#0x40000
000054 600a STR r2,[r1,#0]
;;;188 {
;;;189 case RCC_HSE_ON:
;;;190 /* Set HSEON bit */
;;;191 RCC->CR |= CR_HSEON_Set;
000056 bf04 ITT EQ
000058 6808 LDREQ r0,[r1,#0]
00005a f440f440 ORREQ r0,r0,#0x10000
00005e d006 BEQ |L1.110|
000060 f5b0f5b0 CMP r0,#0x40000
;;;192 break;
;;;193
;;;194 case RCC_HSE_Bypass:
;;;195 /* Set HSEBYP and HSEON bits */
;;;196 RCC->CR |= CR_HSEBYP_Set | CR_HSEON_Set;
;;;197 break;
;;;198
;;;199 default:
;;;200 break;
;;;201 }
;;;202 }
000064 bf18 IT NE
000066 4770 BXNE lr
000068 6808 LDR r0,[r1,#0]
00006a f440f440 ORR r0,r0,#0x50000
|L1.110|
00006e 6008 STR r0,[r1,#0]
000070 4770 BX lr
ENDP
RCC_GetFlagStatus PROC
000072 2200 MOVS r2,#0
000074 0941 LSRS r1,r0,#5
000076 4b92 LDR r3,|L1.704|
000078 2901 CMP r1,#1
00007a bf08 IT EQ
00007c 6819 LDREQ r1,[r3,#0]
00007e d003 BEQ |L1.136|
000080 2902 CMP r1,#2
000082 bf14 ITE NE
000084 6a59 LDRNE r1,[r3,#0x24]
000086 6a19 LDREQ r1,[r3,#0x20]
|L1.136|
000088 f000f000 AND r0,r0,#0x1f
00008c 2301 MOVS r3,#1
00008e fa03fa03 LSL r0,r3,r0
000092 4208 TST r0,r1
000094 bf18 IT NE
000096 2201 MOVNE r2,#1
000098 4610 MOV r0,r2
00009a 4770 BX lr
ENDP
RCC_WaitForHSEStartUp PROC
;;;214 {
;;;215 vu32 StartUpCounter = 0;
00009c 4b88 LDR r3,|L1.704|
00009e 2000 MOVS r0,#0
|L1.160|
0000a0 681a LDR r2,[r3,#0]
0000a2 2100 MOVS r1,#0
0000a4 f412f412 TST r2,#0x20000
0000a8 bf18 IT NE
0000aa 2101 MOVNE r1,#1
;;;216
;;;217 /* Wait till HSE is ready and if Time out is reached exit */
;;;218 while((RCC_GetFlagStatus(RCC_FLAG_HSERDY) == RESET) &&
0000ac b919 CBNZ r1,|L1.182|
0000ae 2880 CMP r0,#0x80
;;;219 (StartUpCounter != HSEStartUp_TimeOut))
;;;220 {
;;;221 StartUpCounter++;
0000b0 bf18 IT NE
0000b2 1c40 ADDNE r0,r0,#1
0000b4 d1f4 BNE |L1.160|
|L1.182|
0000b6 6819 LDR r1,[r3,#0]
0000b8 2000 MOVS r0,#0
0000ba f411f411 TST r1,#0x20000
0000be bf18 IT NE
0000c0 2001 MOVNE r0,#1
;;;222 }
;;;223
;;;224 if(RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET)
0000c2 2800 CMP r0,#0
;;;225 {
;;;226 return SUCCESS;
0000c4 bf18 IT NE
0000c6 2001 MOVNE r0,#1
;;;227 }
;;;228 else
;;;229 {
;;;230 return ERROR;
;;;231 }
;;;232 }
0000c8 4770 BX lr
ENDP
RCC_AdjustHSICalibrationValue PROC
;;;249
;;;250 tmpreg = RCC->CR;
0000ca 4a7d LDR r2,|L1.704|
0000cc 6811 LDR r1,[r2,#0]
;;;251
;;;252 /* Clear HSITRIM[7:3] bits */
;;;253 tmpreg &= CR_HSITRIM_Mask;
0000ce f021f021 BIC r1,r1,#0xf8
;;;254
;;;255 /* Set the HSITRIM[7:3] bits according to HSICalibrationValue value */
;;;256 tmpreg |= (u32)HSICalibrationValue << 3;
0000d2 ea41ea41 ORR r0,r1,r0,LSL #3
;;;257
;;;258 /* Store the new value */
;;;259 RCC->CR = tmpreg;
0000d6 6010 STR r0,[r2,#0]
;;;260 }
0000d8 4770 BX lr
ENDP
RCC_HSICmd PROC
;;;276
;;;277 *(vu32 *) CR_HSION_BB = (u32)NewState;
0000da 497b LDR r1,|L1.712|
0000dc 6008 STR r0,[r1,#0]
;;;278 }
0000de 4770 BX lr
ENDP
RCC_PLLConfig PROC
;;;304
;;;305 tmpreg = RCC->CFGR;
0000e0 4b77 LDR r3,|L1.704|
0000e2 685a LDR r2,[r3,#4]
;;;306
;;;307 /* Clear PLLSRC, PLLXTPRE and PLLMUL[21:18] bits */
;;;308 tmpreg &= CFGR_PLL_Mask;
;;;309
;;;310 /* Set the PLL configuration bits */
;;;311 tmpreg |= RCC_PLLSource | RCC_PLLMul;
0000e4 4308 ORRS r0,r0,r1
0000e6 f422f422 BIC r2,r2,#0x3f0000
0000ea 4310 ORRS r0,r0,r2
;;;312
;;;313 /* Store the new value */
;;;314 RCC->CFGR = tmpreg;
0000ec 6058 STR r0,[r3,#4]
;;;315 }
0000ee 4770 BX lr
ENDP
RCC_PLLCmd PROC
;;;330
;;;331 *(vu32 *) CR_PLLON_BB = (u32)NewState;
0000f0 4975 LDR r1,|L1.712|
0000f2 6608 STR r0,[r1,#0x60]
;;;332 }
0000f4 4770 BX lr
ENDP
RCC_SYSCLKConfig PROC
;;;351
;;;352 tmpreg = RCC->CFGR;
0000f6 4a72 LDR r2,|L1.704|
0000f8 6851 LDR r1,[r2,#4]
;;;353
;;;354 /* Clear SW[1:0] bits */
;;;355 tmpreg &= CFGR_SW_Mask;
0000fa f021f021 BIC r1,r1,#3
;;;356
;;;357 /* Set SW[1:0] bits according to RCC_SYSCLKSource value */
;;;358 tmpreg |= RCC_SYSCLKSource;
0000fe 4308 ORRS r0,r0,r1
;;;359
;;;360 /* Store the new value */
;;;361 RCC->CFGR = tmpreg;
000100 6050 STR r0,[r2,#4]
;;;362 }
000102 4770 BX lr
ENDP
RCC_GetSYSCLKSource PROC
;;;376 {
;;;377 return ((u8)(RCC->CFGR & CFGR_SWS_Mask));
000104 486e LDR r0,|L1.704|
000106 6840 LDR r0,[r0,#4]
000108 f000f000 AND r0,r0,#0xc
;;;378 }
00010c 4770 BX lr
ENDP
RCC_HCLKConfig PROC
;;;404
;;;405 tmpreg = RCC->CFGR;
00010e 4a6c LDR r2,|L1.704|
000110 6851 LDR r1,[r2,#4]
;;;406
;;;407 /* Clear HPRE[7:4] bits */
;;;408 tmpreg &= CFGR_HPRE_Reset_Mask;
000112 f021f021 BIC r1,r1,#0xf0
;;;409
;;;410 /* Set HPRE[7:4] bits according to RCC_HCLK value */
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