📄 stm32f10x_nvic.txt
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; generated by ARM/Thumb C/C++ Compiler with Crescent Bay VAST 10.7u+w+:x ARM NEON, RVCT3.1 [Build 903] for uVision
; commandline ArmCC [--debug -c --asm --interleave -o..\obj\stm32f10x_nvic.o --depend=..\obj\stm32f10x_nvic.d --device=DARMSTM -O3 -Otime -I..\..\LAB6 -I..\..\library\inc -IC:\Keil\ARM\INC\ST\STM32F10x -DVECT_TAB_FLASH --omf_browse=..\obj\stm32f10x_nvic.crf ..\..\library\src\stm32f10x_nvic.c]
THUMB
AREA ||.text||, CODE, READONLY, ALIGN=2
NVIC_DeInit PROC
;;;44
;;;45 NVIC->Disable[0] = 0xFFFFFFFF;
000000 f04ff04f MOV r0,#0xffffffff
000004 f04ff04f MOV r3,#0xe000e000
;;;46 NVIC->Disable[1] = 0x000007FF;
000008 0d41 LSRS r1,r0,#21
;;;47 NVIC->Clear[0] = 0xFFFFFFFF;
00000a f8c3f8c3 STR r0,[r3,#0x180]
;;;48 NVIC->Clear[1] = 0x000007FF;
00000e f8c3f8c3 STR r1,[r3,#0x184]
;;;49
;;;50 for(index = 0; index < 0x0B; index++)
;;;51 {
;;;52 NVIC->Priority[index] = 0x00000000;
000012 2200 MOVS r2,#0
;;;53 }
000014 f8c3f8c3 STR r2,[r3,#0x400]
000018 f8c3f8c3 STR r1,[r3,#0x284]
00001c f8c3f8c3 STR r0,[r3,#0x280]
000020 2101 MOVS r1,#1
000022 4608 MOV r0,r1
|L1.36|
000024 eb03eb03 ADD r12,r3,r1,LSL #2
000028 1c49 ADDS r1,r1,#1
00002a f8ccf8cc STR r2,[r12,#0x400]
00002e eb03eb03 ADD r12,r3,r1,LSL #2
000032 1c49 ADDS r1,r1,#1
000034 1c80 ADDS r0,r0,#2
000036 f8ccf8cc STR r2,[r12,#0x400]
00003a 280b CMP r0,#0xb
00003c d3f2 BCC |L1.36|
;;;54 }
00003e 4770 BX lr
ENDP
NVIC_SCBDeInit PROC
;;;67
;;;68 SCB->IRQControlState = 0x0A000000;
000040 48b0 LDR r0,|L1.772|
000042 f04ff04f MOV r1,#0xa000000
000046 6001 STR r1,[r0,#0]
;;;69 SCB->ExceptionTableOffset = 0x00000000;
000048 2100 MOVS r1,#0
00004a 6041 STR r1,[r0,#4]
;;;70 SCB->AIRC = AIRC_VECTKEY_MASK;
00004c 4aae LDR r2,|L1.776|
00004e 6082 STR r2,[r0,#8]
;;;71 SCB->SysCtrl = 0x00000000;
000050 60c1 STR r1,[r0,#0xc]
;;;72 SCB->ConfigCtrl = 0x00000000;
000052 6101 STR r1,[r0,#0x10]
;;;73 for(index = 0; index < 0x03; index++)
;;;74 {
;;;75 SCB->SystemPriority[index] = 0;
000054 6141 STR r1,[r0,#0x14]
000056 6181 STR r1,[r0,#0x18]
;;;76 }
;;;77 SCB->SysHandlerCtrl = 0x00000000;
000058 61c1 STR r1,[r0,#0x1c]
00005a 6201 STR r1,[r0,#0x20]
;;;78 SCB->ConfigFaultStatus = 0xFFFFFFFF;
00005c 1741 ASRS r1,r0,#29
00005e 6241 STR r1,[r0,#0x24]
;;;79 SCB->HardFaultStatus = 0xFFFFFFFF;
000060 6281 STR r1,[r0,#0x28]
;;;80 SCB->DebugFaultStatus = 0xFFFFFFFF;
000062 62c1 STR r1,[r0,#0x2c]
;;;81 }
000064 4770 BX lr
ENDP
NVIC_PriorityGroupConfig PROC
;;;107 /* Set the PRIGROUP[10:8] bits according to NVIC_PriorityGroup value */
;;;108 SCB->AIRC = AIRC_VECTKEY_MASK | NVIC_PriorityGroup;
000066 f040f040 ORR r0,r0,#0x1fa0000
00006a 49a8 LDR r1,|L1.780|
00006c f040f040 ORR r0,r0,#0x4000000
000070 6008 STR r0,[r1,#0]
;;;109 }
000072 4770 BX lr
ENDP
NVIC_Init PROC
;;;121 void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct)
;;;122 {
000074 b470 PUSH {r4-r6}
;;;123 u32 tmppriority = 0x00, tmpreg = 0x00, tmpmask = 0x00;
;;;124 u32 tmppre = 0, tmpsub = 0x0F;
;;;125
;;;126 /* Check the parameters */
;;;127 assert(IS_FUNCTIONAL_STATE(NVIC_InitStruct->NVIC_IRQChannelCmd));
;;;128 assert(IS_NVIC_IRQ_CHANNEL(NVIC_InitStruct->NVIC_IRQChannel));
;;;129 assert(IS_NVIC_PREEMPTION_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority));
;;;130 assert(IS_NVIC_SUB_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelSubPriority));
;;;131
;;;132 if (NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE)
000076 78c2 LDRB r2,[r0,#3]
000078 7801 LDRB r1,[r0,#0]
00007a f04ff04f MOV r12,#0xf
00007e f04ff04f MOV r5,#0xe000e000
000082 2601 MOVS r6,#1
000084 b382 CBZ r2,|L1.232|
;;;133 {
;;;134 /* Compute the Corresponding IRQ Priority --------------------------------*/
;;;135 tmppriority = (0x700 - (SCB->AIRC & (u32)0x700))>> 0x08;
000086 f8d5f8d5 LDR r2,[r5,#0xd0c]
;;;136 tmppre = (0x4 - tmppriority);
;;;137 tmpsub = tmpsub >> tmppriority;
;;;138
;;;139 tmppriority = (u32)NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << tmppre;
;;;140 tmppriority |= NVIC_InitStruct->NVIC_IRQChannelSubPriority & tmpsub;
00008a 7884 LDRB r4,[r0,#2]
00008c f402f402 AND r2,r2,#0x700
000090 f5c2f5c2 RSB r2,r2,#0x700
000094 0a12 LSRS r2,r2,#8
000096 f1c2f1c2 RSB r3,r2,#4
00009a fa2cfa2c LSR r2,r12,r2
00009e f890f890 LDRB r12,[r0,#1]
0000a2 4014 ANDS r4,r4,r2
0000a4 fa0cfa0c LSL r2,r12,r3
0000a8 4322 ORRS r2,r2,r4
0000aa 0113 LSLS r3,r2,#4
;;;141
;;;142 tmppriority = tmppriority << 0x04;
;;;143 tmppriority = ((u32)tmppriority) << ((NVIC_InitStruct->NVIC_IRQChannel & (u8)0x03) * 0x08);
0000ac 078a LSLS r2,r1,#30
0000ae 0ed2 LSRS r2,r2,#27
0000b0 fa03fa03 LSL r12,r3,r2
;;;144
;;;145 tmpreg = NVIC->Priority[(NVIC_InitStruct->NVIC_IRQChannel >> 0x02)];
0000b4 f021f021 BIC r1,r1,#3
0000b8 194b ADDS r3,r1,r5
0000ba f8d3f8d3 LDR r4,[r3,#0x400]
;;;146 tmpmask = (u32)0xFF << ((NVIC_InitStruct->NVIC_IRQChannel & (u8)0x03) * 0x08);
0000be 21ff MOVS r1,#0xff
0000c0 4091 LSLS r1,r1,r2
;;;147 tmpreg &= ~tmpmask;
0000c2 ea24ea24 BIC r2,r4,r1
;;;148 tmppriority &= tmpmask;
0000c6 ea0cea0c AND r1,r12,r1
;;;149 tmpreg |= tmppriority;
0000ca 4311 ORRS r1,r1,r2
;;;150
;;;151 NVIC->Priority[(NVIC_InitStruct->NVIC_IRQChannel >> 0x02)] = tmpreg;
;;;152
;;;153 /* Enable the Selected IRQ Channels --------------------------------------*/
;;;154 NVIC->Enable[(NVIC_InitStruct->NVIC_IRQChannel >> 0x05)] =
0000cc f8c3f8c3 STR r1,[r3,#0x400]
0000d0 7800 LDRB r0,[r0,#0]
0000d2 0941 LSRS r1,r0,#5
0000d4 f000f000 AND r0,r0,#0x1f
0000d8 eb05eb05 ADD r1,r5,r1,LSL #2
0000dc fa06fa06 LSL r0,r6,r0
0000e0 f8c1f8c1 STR r0,[r1,#0x100]
;;;155 (u32)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (u8)0x1F);
;;;156 }
;;;157 else
;;;158 {
;;;159 /* Disable the Selected IRQ Channels -------------------------------------*/
;;;160 NVIC->Disable[(NVIC_InitStruct->NVIC_IRQChannel >> 0x05)] =
;;;161 (u32)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (u8)0x1F);
;;;162 }
;;;163 }
0000e4 bc70 POP {r4-r6}
0000e6 4770 BX lr
|L1.232|
0000e8 e7ff B |L1.234|
|L1.234|
0000ea f001f001 AND r0,r1,#0x1f
0000ee fa06fa06 LSL r0,r6,r0
0000f2 0949 LSRS r1,r1,#5
0000f4 eb05eb05 ADD r1,r5,r1,LSL #2
0000f8 f8c1f8c1 STR r0,[r1,#0x180]
0000fc bc70 POP {r4-r6}
0000fe 4770 BX lr
ENDP
NVIC_StructInit PROC
;;;175 /* NVIC_InitStruct members default value */
;;;176 NVIC_InitStruct->NVIC_IRQChannel = 0x00;
000100 2100 MOVS r1,#0
000102 7001 STRB r1,[r0,#0]
;;;177 NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority = 0x00;
000104 7041 STRB r1,[r0,#1]
;;;178 NVIC_InitStruct->NVIC_IRQChannelSubPriority = 0x00;
000106 7081 STRB r1,[r0,#2]
;;;179 NVIC_InitStruct->NVIC_IRQChannelCmd = DISABLE;
000108 70c1 STRB r1,[r0,#3]
;;;180 }
00010a 4770 BX lr
ENDP
NVIC_SETPRIMASK PROC
;;;190 {
;;;191 __SETPRIMASK();
00010c f7fff7ff B.W __SETPRIMASK
;;;192 }
ENDP
NVIC_RESETPRIMASK PROC
;;;202 {
;;;203 __RESETPRIMASK();
000110 f7fff7ff B.W __RESETPRIMASK
;;;204 }
ENDP
NVIC_SETFAULTMASK PROC
;;;214 {
;;;215 __SETFAULTMASK();
000114 f7fff7ff B.W __SETFAULTMASK
;;;216 }
ENDP
NVIC_RESETFAULTMASK PROC
;;;226 {
;;;227 __RESETFAULTMASK();
000118 f7fff7ff B.W __RESETFAULTMASK
;;;228 }
ENDP
NVIC_BASEPRICONFIG PROC
;;;242
;;;243 __BASEPRICONFIG(NewPriority << 0x04);
00011c 0100 LSLS r0,r0,#4
00011e f7fff7ff B.W __BASEPRICONFIG
;;;244 }
ENDP
NVIC_GetBASEPRI PROC
;;;254 {
;;;255 return (__GetBASEPRI());
000122 f7fff7ff B.W __GetBASEPRI
;;;256 }
ENDP
NVIC_GetCurrentPendingIRQChannel PROC
;;;265 u16 NVIC_GetCurrentPendingIRQChannel(void)
;;;266 {
000126 4877 LDR r0,|L1.772|
;;;267 return ((u16)((SCB->IRQControlState & (u32)0x003FF000) >> 0x0C));
000128 6800 LDR r0,[r0,#0]
00012a f3c0f3c0 UBFX r0,r0,#12,#10
;;;268 }
00012e 4770 BX lr
ENDP
NVIC_GetIRQChannelPendingBitStatus PROC
;;;285
;;;286 tmp = ((u32)0x01 << (NVIC_IRQChannel & (u32)0x1F));
000130 f000f000 AND r2,r0,#0x1f
000134 2301 MOVS r3,#1
000136 fa03fa03 LSL r2,r3,r2
00013a 2100 MOVS r1,#0
;;;287
;;;288 if (((NVIC->Set[(NVIC_IRQChannel >> 0x05)]) & tmp) == tmp)
00013c 0940 LSRS r0,r0,#5
00013e f04ff04f MOV r3,#0xe000e000
000142 eb03eb03 ADD r0,r3,r0,LSL #2
000146 f8d0f8d0 LDR r0,[r0,#0x200]
00014a ea32ea32 BICS r0,r2,r0
;;;289 {
;;;290 pendingirqstatus = SET;
00014e bf08 IT EQ
000150 2101 MOVEQ r1,#1
;;;291 }
;;;292 else
;;;293 {
;;;294 pendingirqstatus = RESET;
;;;295 }
;;;296 return pendingirqstatus;
000152 4608 MOV r0,r1
;;;297 }
000154 4770 BX lr
ENDP
NVIC_SetIRQChannelPendingBit PROC
;;;306 void NVIC_SetIRQChannelPendingBit(u8 NVIC_IRQChannel)
;;;307 {
000156 496e LDR r1,|L1.784|
;;;308 /* Check the parameters */
;;;309 assert(IS_NVIC_IRQ_CHANNEL(NVIC_IRQChannel));
;;;310
;;;311 *(u32*)0xE000EF00 = (u32)NVIC_IRQChannel;
;;;312 }
000158 6008 STR r0,[r1,#0]
00015a 4770 BX lr
ENDP
NVIC_ClearIRQChannelPendingBit PROC
;;;325
;;;326 NVIC->Clear[(NVIC_IRQChannel >> 0x05)] = (u32)0x01 << (NVIC_IRQChannel & (u32)0x1F);
00015c f000f000 AND r1,r0,#0x1f
000160 2201 MOVS r2,#1
000162 fa02fa02 LSL r1,r2,r1
000166 0940 LSRS r0,r0,#5
000168 f04ff04f MOV r2,#0xe000e000
00016c eb02eb02 ADD r0,r2,r0,LSL #2
;;;327 }
000170 f8c0f8c0 STR r1,[r0,#0x280]
000174 4770 BX lr
ENDP
NVIC_GetCurrentActiveHandler PROC
;;;337 u16 NVIC_GetCurrentActiveHandler(void)
;;;338 {
000176 4863 LDR r0,|L1.772|
;;;339 return ((u16)(SCB->IRQControlState & (u32)0x3FF));
000178 6800 LDR r0,[r0,#0]
00017a f3c0f3c0 UBFX r0,r0,#0,#10
;;;340 }
00017e 4770 BX lr
ENDP
NVIC_GetIRQChannelActiveBitStatus PROC
;;;357
;;;358 tmp = ((u32)0x01 << (NVIC_IRQChannel & (u32)0x1F));
000180 f000f000 AND r2,r0,#0x1f
000184 2301 MOVS r3,#1
000186 fa03fa03 LSL r2,r3,r2
00018a 2100 MOVS r1,#0
;;;359
;;;360 if (((NVIC->Active[(NVIC_IRQChannel >> 0x05)]) & tmp) == tmp )
00018c 0940 LSRS r0,r0,#5
00018e f04ff04f MOV r3,#0xe000e000
000192 eb03eb03 ADD r0,r3,r0,LSL #2
000196 f8d0f8d0 LDR r0,[r0,#0x300]
00019a ea32ea32 BICS r0,r2,r0
;;;361 {
;;;362 activeirqstatus = SET;
00019e bf08 IT EQ
0001a0 2101 MOVEQ r1,#1
;;;363 }
;;;364 else
;;;365 {
;;;366 activeirqstatus = RESET;
;;;367 }
;;;368 return activeirqstatus;
0001a2 4608 MOV r0,r1
;;;369 }
0001a4 4770 BX lr
ENDP
NVIC_GetCPUID PROC
;;;379 u32 NVIC_GetCPUID(void)
;;;380 {
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