📄 stm32f10x_gpio.txt
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; generated by ARM/Thumb C/C++ Compiler with Crescent Bay VAST 10.7u+w+:x ARM NEON, RVCT3.1 [Build 903] for uVision
; commandline ArmCC [--debug -c --asm --interleave -o..\obj\stm32f10x_gpio.o --depend=..\obj\stm32f10x_gpio.d --device=DARMSTM -O3 -Otime -I..\..\LAB6 -I..\..\library\inc -IC:\Keil\ARM\INC\ST\STM32F10x -DVECT_TAB_FLASH --omf_browse=..\obj\stm32f10x_gpio.crf ..\..\library\src\stm32f10x_gpio.c]
THUMB
AREA ||.text||, CODE, READONLY, ALIGN=2
GPIO_DeInit PROC
;;;57 {
;;;58 switch (*(u32*)&GPIOx)
000000 4a92 LDR r2,|L1.588|
000002 b510 PUSH {r4,lr}
000004 1a81 SUBS r1,r0,r2
000006 4290 CMP r0,r2
000008 d02e BEQ |L1.104|
00000a dc12 BGT |L1.50|
00000c f1a0f1a0 SUB r0,r0,#0x40000000
000010 f5b0f5b0 SUBS r0,r0,#0x10800
000014 d01e BEQ |L1.84|
000016 f5b0f5b0 CMP r0,#0x400
;;;59 {
;;;60 case GPIOA_BASE:
;;;61 RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, ENABLE);
;;;62 RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, DISABLE);
;;;63 break;
;;;64
;;;65 case GPIOB_BASE:
;;;66 RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOB, ENABLE);
;;;67 RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOB, DISABLE);
;;;68 break;
;;;69
;;;70 case GPIOC_BASE:
;;;71 RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOC, ENABLE);
;;;72 RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOC, DISABLE);
;;;73 break;
;;;74
;;;75 case GPIOD_BASE:
;;;76 RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOD, ENABLE);
;;;77 RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOD, DISABLE);
;;;78 break;
;;;79
;;;80 case GPIOE_BASE:
;;;81 RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOE, ENABLE);
;;;82 RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOE, DISABLE);
;;;83 break;
;;;84
;;;85 default:
;;;86 break;
;;;87 }
;;;88 }
00001a bf18 IT NE
00001c bd10 POPNE {r4,pc}
00001e 2101 MOVS r1,#1
000020 2008 MOVS r0,#8
000022 f7fff7ff BL RCC_APB2PeriphResetCmd
000026 2100 MOVS r1,#0
000028 e8bde8bd POP {r4,lr}
00002c 2008 MOVS r0,#8
00002e f7fff7ff B.W RCC_APB2PeriphResetCmd
|L1.50|
000032 f5b1f5b1 CMP r1,#0x400
000036 d021 BEQ |L1.124|
000038 f5b1f5b1 CMP r1,#0x800
00003c bf18 IT NE
00003e bd10 POPNE {r4,pc}
000040 2101 MOVS r1,#1
000042 2040 MOVS r0,#0x40
000044 f7fff7ff BL RCC_APB2PeriphResetCmd
000048 2100 MOVS r1,#0
00004a e8bde8bd POP {r4,lr}
00004e 2040 MOVS r0,#0x40
000050 f7fff7ff B.W RCC_APB2PeriphResetCmd
|L1.84|
000054 2101 MOVS r1,#1
000056 2004 MOVS r0,#4
000058 f7fff7ff BL RCC_APB2PeriphResetCmd
00005c 2100 MOVS r1,#0
00005e e8bde8bd POP {r4,lr}
000062 2004 MOVS r0,#4
000064 f7fff7ff B.W RCC_APB2PeriphResetCmd
|L1.104|
000068 2101 MOVS r1,#1
00006a 2010 MOVS r0,#0x10
00006c f7fff7ff BL RCC_APB2PeriphResetCmd
000070 2100 MOVS r1,#0
000072 e8bde8bd POP {r4,lr}
000076 2010 MOVS r0,#0x10
000078 f7fff7ff B.W RCC_APB2PeriphResetCmd
|L1.124|
00007c 2101 MOVS r1,#1
00007e 2020 MOVS r0,#0x20
000080 f7fff7ff BL RCC_APB2PeriphResetCmd
000084 2100 MOVS r1,#0
000086 e8bde8bd POP {r4,lr}
00008a 2020 MOVS r0,#0x20
00008c f7fff7ff B.W RCC_APB2PeriphResetCmd
ENDP
GPIO_AFIODeInit PROC
;;;99 void GPIO_AFIODeInit(void)
;;;100 {
000090 b510 PUSH {r4,lr}
;;;101 RCC_APB2PeriphResetCmd(RCC_APB2Periph_AFIO, ENABLE);
000092 2101 MOVS r1,#1
000094 4608 MOV r0,r1
000096 f7fff7ff BL RCC_APB2PeriphResetCmd
;;;102 RCC_APB2PeriphResetCmd(RCC_APB2Periph_AFIO, DISABLE);
00009a 2100 MOVS r1,#0
00009c e8bde8bd POP {r4,lr}
0000a0 2001 MOVS r0,#1
0000a2 f7fff7ff B.W RCC_APB2PeriphResetCmd
;;;103 }
ENDP
GPIO_Init PROC
;;;116 void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct)
;;;117 {
0000a6 e92de92d PUSH {r4-r8}
;;;118 u32 currentmode = 0x00, currentpin = 0x00, pinpos = 0x00, pos = 0x00;
;;;119 u32 tmpreg = 0x00, pinmask = 0x00;
;;;120
;;;121 /* Check the parameters */
;;;122 assert(IS_GPIO_MODE(GPIO_InitStruct->GPIO_Mode));
;;;123 assert(IS_GPIO_PIN(GPIO_InitStruct->GPIO_Pin));
;;;124
;;;125 /*---------------------------- GPIO Mode Configuration -----------------------*/
;;;126 currentmode = ((u32)GPIO_InitStruct->GPIO_Mode) & ((u32)0x0F);
0000aa 78cb LDRB r3,[r1,#3]
0000ac 2200 MOVS r2,#0
;;;127
;;;128 if ((((u32)GPIO_InitStruct->GPIO_Mode) & ((u32)0x10)) != 0x00)
0000ae f013f013 TST r3,#0x10
0000b2 f003f003 AND r4,r3,#0xf
;;;129 {
;;;130 /* Check the parameters */
;;;131 assert(IS_GPIO_SPEED(GPIO_InitStruct->GPIO_Speed));
;;;132 /* Output mode */
;;;133 currentmode |= (u32)GPIO_InitStruct->GPIO_Speed;
0000b6 bf1c ITT NE
0000b8 788b LDRBNE r3,[r1,#2]
0000ba 431c ORRNE r4,r4,r3
;;;134 }
;;;135
;;;136 /*---------------------------- GPIO CRL Configuration ------------------------*/
;;;137 /* Configure the eight low port pins */
;;;138 if (((u32)GPIO_InitStruct->GPIO_Pin & ((u32)0x00FF)) != 0x00)
0000bc 880b LDRH r3,[r1,#0]
0000be 250f MOVS r5,#0xf
0000c0 f013f013 TST r3,#0xff
0000c4 f04ff04f MOV r6,#1
0000c8 d022 BEQ |L1.272|
;;;139 {
;;;140 tmpreg = GPIOx->CRL;
0000ca 6807 LDR r7,[r0,#0]
|L1.204|
;;;141
;;;142 for (pinpos = 0x00; pinpos < 0x08; pinpos++)
;;;143 {
;;;144 pos = ((u32)0x01) << pinpos;
;;;145 /* Get the port pins position */
;;;146 currentpin = (GPIO_InitStruct->GPIO_Pin) & pos;
0000cc f8b1f8b1 LDRH r12,[r1,#0]
0000d0 fa06fa06 LSL r3,r6,r2
0000d4 ea0cea0c AND r12,r12,r3
;;;147
;;;148 if (currentpin == pos)
0000d8 459c CMP r12,r3
0000da d115 BNE |L1.264|
0000dc ea4fea4f LSL r12,r2,#2
;;;149 {
;;;150 pos = pinpos << 2;
;;;151 /* Clear the corresponding low control register bits */
;;;152 pinmask = ((u32)0x0F) << pos;
0000e0 fa05fa05 LSL r8,r5,r12
;;;153 tmpreg &= ~pinmask;
0000e4 ea27ea27 BIC r7,r7,r8
;;;154
;;;155 /* Write the mode configuration in the corresponding bits */
;;;156 tmpreg |= (currentmode << pos);
0000e8 fa04fa04 LSL r12,r4,r12
0000ec ea4cea4c ORR r7,r12,r7
;;;157
;;;158 /* Reset the corresponding ODR bit */
;;;159 if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD)
0000f0 f891f891 LDRB r12,[r1,#3]
0000f4 f1bcf1bc CMP r12,#0x28
;;;160 {
;;;161 GPIOx->BRR = (((u32)0x01) << pinpos);
0000f8 bf08 IT EQ
0000fa 6143 STREQ r3,[r0,#0x14]
;;;162 }
;;;163 /* Set the corresponding ODR bit */
;;;164 if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU)
0000fc f891f891 LDRB r12,[r1,#3]
000100 f1bcf1bc CMP r12,#0x48
;;;165 {
;;;166 GPIOx->BSRR = (((u32)0x01) << pinpos);
000104 bf08 IT EQ
000106 6103 STREQ r3,[r0,#0x10]
|L1.264|
000108 1c52 ADDS r2,r2,#1
00010a 2a08 CMP r2,#8
00010c d3de BCC |L1.204|
;;;167 }
;;;168 }
;;;169 }
;;;170 GPIOx->CRL = tmpreg;
00010e 6007 STR r7,[r0,#0]
|L1.272|
;;;171 tmpreg = 0;
;;;172 }
;;;173
;;;174 /*---------------------------- GPIO CRH Configuration ------------------------*/
;;;175 /* Configure the eight high port pins */
;;;176 if (GPIO_InitStruct->GPIO_Pin > 0x00FF)
000110 880a LDRH r2,[r1,#0]
000112 2aff CMP r2,#0xff
;;;177 {
;;;178 tmpreg = GPIOx->CRH;
;;;179 for (pinpos = 0x00; pinpos < 0x08; pinpos++)
;;;180 {
;;;181 pos = (((u32)0x01) << (pinpos + 0x08));
;;;182 /* Get the port pins position */
;;;183 currentpin = ((GPIO_InitStruct->GPIO_Pin) & pos);
;;;184 if (currentpin == pos)
;;;185 {
;;;186 pos = pinpos << 2;
;;;187 /* Clear the corresponding high control register bits */
;;;188 pinmask = ((u32)0x0F) << pos;
;;;189 tmpreg &= ~pinmask;
;;;190
;;;191 /* Write the mode configuration in the corresponding bits */
;;;192 tmpreg |= (currentmode << pos);
;;;193
;;;194 /* Reset the corresponding ODR bit */
;;;195 if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD)
;;;196 {
;;;197 GPIOx->BRR = (((u32)0x01) << (pinpos + 0x08));
;;;198 }
;;;199 /* Set the corresponding ODR bit */
;;;200 if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU)
;;;201 {
;;;202 GPIOx->BSRR = (((u32)0x01) << (pinpos + 0x08));
;;;203 }
;;;204 }
;;;205 }
;;;206 GPIOx->CRH = tmpreg;
;;;207 }
;;;208 }
000114 bf9c ITT LS
000116 e8bde8bd POPLS {r4-r8}
00011a 4770 BXLS lr
00011c 6847 LDR r7,[r0,#4]
00011e 2200 MOVS r2,#0
|L1.288|
000120 f102f102 ADD r3,r2,#8
000124 f8b1f8b1 LDRH r12,[r1,#0]
000128 fa06fa06 LSL r3,r6,r3
00012c ea0cea0c AND r12,r12,r3
000130 459c CMP r12,r3
000132 d115 BNE |L1.352|
000134 ea4fea4f LSL r12,r2,#2
000138 fa05fa05 LSL r8,r5,r12
00013c ea27ea27 BIC r7,r7,r8
000140 fa04fa04 LSL r12,r4,r12
000144 ea4cea4c ORR r7,r12,r7
000148 f891f891 LDRB r12,[r1,#3]
00014c f1bcf1bc CMP r12,#0x28
000150 bf08 IT EQ
000152 6143 STREQ r3,[r0,#0x14]
000154 f891f891 LDRB r12,[r1,#3]
000158 f1bcf1bc CMP r12,#0x48
00015c bf08 IT EQ
00015e 6103 STREQ r3,[r0,#0x10]
|L1.352|
000160 1c52 ADDS r2,r2,#1
000162 2a08 CMP r2,#8
000164 d3dc BCC |L1.288|
000166 6047 STR r7,[r0,#4]
000168 e8bde8bd POP {r4-r8}
00016c 4770 BX lr
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