asyfifo_reg.h

来自「AMLOGIC DPF source code」· C头文件 代码 · 共 93 行

/***************************************************************************
* Copyright (c) 2002 AMLOGIC, Inc.
* All rights reserved.
*
* Description: ARM Memory/Register Map
*
* Input      :
*
* Output     :
*
****************************************************************************/

#ifndef TEST_H
#define TEST_H
// -----------------------------------------------
// Useful MPEG domain registers
// -----------------------------------------------
   #define INT_IIS                    21
   #define INT_ASYNC_FIFO_FLUSH       19
   #define INT_ASYNC_FIFO_FILL        18
   #define INT_ABUF_RD                17
   #define INT_ABUF_WR                16
   #define INT_IR_DEC_IRQ             15	// IR NEC Frame Decoder IRQ
   #define INT_BLKMV                  14
   #define INT_SMART_MEDIA            13	// Smart Media IRQ
   #define INT_IDE                    12
   #define INT_PIT2                   11
   #define INT_PIT1                   10
   #define INT_SPDIF_IRQ               7      // SPDIF
   #define INT_RTC_IRQ                 6	// Real Time Clock
   #define INT_IRQ14                   4
   #define INT_VSYNC                   3
   #define INT_HSYNC                   2
   #define INT_MAILBOX                 1

   #define INT_GPIO_BLOCK_SYNC  19

// -----------------------------------------------
// AML3280: Peripherals Module #defines
// -----------------------------------------------
#ifdef AML3280
    
    #define     PERIPHS_CTLREG5        0x14
    #define         THOMSON_DIS_START_SRCH  1
    #define         THOMSON_PATH_EN         0
    
    // DMA start address.
    #define IIS_DATA_FIFO_CTRL              0x2c0
        #define IIS_FIFO_SOFT_RESET         31      // Soft reset
        #define IIS_CLR_ERR                 30      // clear error
        #define IIS_FIFO_COUNT_LSB          16  
        #define IIS_USE_ASYNC_LOGIC         15
        #define IIS_SKIP_SIZE_MSB           13
        #define IIS_SKIP_SIZE_LSB           4
        #define IIS_FLUSH_EN_BIT            3   // 1 : enable FLUSH FIFO.
        #define IIS_FILL_EN_BIT             2   // 1 : enable PUSH FIFO.
        #define IIS_FIFO_ENDIAN_MSB         1   
        #define IIS_FIFO_ENDIAN_LSB         1   
    
    #define ASYNC_FIFO0_REG     0x2e0
    #define ASYNC_FIFO1_REG     0x2e4
        #define ASYNC_FIFO_FLUSH_STATUS     31
        #define ASYNC_FIFO_ERR              30
        #define ASYNC_FIFO_FIFO_EMPTY       29
        #define ASYNC_FIFO_TO_HIU           24
        #define ASYNC_FIFO_FLUSH            23
        #define ASYNC_FIFO_RESET            22
        #define ASYNC_FIFO_WRAP_EN          21
        #define ASYNC_FIFO_FLUSH_EN         20
        #define ASYNC_FIFO_RESIDUAL_MSB     19
        #define ASYNC_FIFO_RESIDUAL_LSB     15
        #define ASYNC_FIFO_FLUSH_CNT_MSB    14
        #define ASYNC_FIFO_FLUSH_CNT_LSB    0
    
    #define ASYNC_FIFO2_REG     0x2e8
        #define ASYNC_FIFO_FIFO_FULL        26
        #define ASYNC_FIFO_FILL_STATUS      25
        #define ASYNC_FIFO_SOURCE_MSB       24
        #define ASYNC_FIFO_SOURCE_LSB       23
        #define ASYNC_FIFO_ENDIAN_MSB       22
        #define ASYNC_FIFO_ENDIAN_LSB       21
        #define ASYNC_FIFO_FILL_EN          20
        #define ASYNC_FIFO_FILL_CNT_MSB     19
        #define ASYNC_FIFO_FILL_CNT_LSB     0
    #define ASYNC_FIFO3_REG     0x2ec
        #define ASYNC_FLUSH_SIZE_IRQ_MSB    15
        #define ASYNC_FLUSH_SIZE_IRQ_LSB    0
#endif


#endif