📄 regs.h
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#ifndef REGS_H
#define REGS_H
/******************************************************************************
*
* Copyright (C) 2005 Freescale Semiconductor, Inc.
* All Rights Reserved
*
* Filename: regs.h
*
* Revision:
*
* Functions: Register definition file for S08DZ60
*
* Description:
*
* Notes:
*
******************************************************************************/
#if defined(S08)
#if defined(S08DZ60)
//#if defined(HEADER)
//#include <HC9S08AW60.h>
#else
/*
#define SCI1BDH (*(volatile char *)0x0038 )
#define SCI1BDL (*(volatile char *)0x0039 )
#define SCI1C1 (*(volatile char *)0x003A )
#define SCI1C2 (*(volatile char *)0x003B )
#define SCI1S1 (*(volatile char *)0x003C )
#define SCI1S2 (*(volatile char *)0x003D )
#define SCI1C3 (*(volatile char *)0x003E )
#define SCI1D (*(volatile char *)0x003F )
#define SCI2BDH (*(volatile char *)0x0040 )
#define SCI2BDL (*(volatile char *)0x0041 )
#define SCI2C1 (*(volatile char *)0x0042 )
#define SCI2C2 (*(volatile char *)0x0043 )
#define SCI2S1 (*(volatile char *)0x0044 )
#define SCI2S2 (*(volatile char *)0x0045 )
#define SCI2C3 (*(volatile char *)0x0046 )
#define SCI2D (*(volatile char *)0x0047 )
#define TPM1SC (*(volatile char *)0x0020 )
#define TPM1CNT (*(volatile int *)0x0021 )
#define TPM1CNTH (*(volatile char *)0x0021 )
#define TPM1CNTL (*(volatile char *)0x0022 )
#define TPM1MOD (*(volatile int *)0x0023 )
#define TPM1MODH (*(volatile char *)0x0023 )
#define TPM1MODL (*(volatile char *)0x0024 )
#define TPM1C0SC (*(volatile char *)0x0025 )
#define TPM1C0V (*(volatile int *)0x0026 )
#define TPM1C0VH (*(volatile char *)0x0026 )
#define TPM1C0VL (*(volatile char *)0x0027 )
#define TPM1C1SC (*(volatile char *)0x0028 )
#define TPM1C1V (*(volatile int *)0x0029 )
#define TPM1C1VH (*(volatile char *)0x0029 )
#define TPM1C1VL (*(volatile char *)0x002A )
#define TPM1C2SC (*(volatile char *)0x002B )
#define TPM1C2V (*(volatile int *)0x002C )
#define TPM1C2VH (*(volatile char *)0x002C )
#define TPM1C2VL (*(volatile char *)0x002D )
#define TPM1C3SC (*(volatile char *)0x002E )
#define TPM1C3V (*(volatile int *)0x002F )
#define TPM1C3VH (*(volatile char *)0x002F )
#define TPM1C3VL (*(volatile char *)0x0030 )
#define TPM1C4SC (*(volatile char *)0x0031 )
#define TPM1C4V (*(volatile int *)0x0032 )
#define TPM1C4VH (*(volatile char *)0x0032 )
#define TPM1C4VL (*(volatile char *)0x0033 )
#define TPM1C5SC (*(volatile char *)0x0034 )
#define TPM1C5V (*(volatile int *)0x0035 )
#define TPM1C5VH (*(volatile char *)0x0035 )
#define TPM1C5VL (*(volatile char *)0x0036 )
#define TPM2SC (*(volatile char *)0x0060 )
#define TPM2CNT (*(volatile int *)0x0061 )
#define TPM2CNTH (*(volatile char *)0x0061 )
#define TPM2CNTL (*(volatile char *)0x0062 )
#define TPM2MOD (*(volatile int *)0x0063 )
#define TPM2MODH (*(volatile char *)0x0063 )
#define TPM2MODL (*(volatile char *)0x0064 )
#define TPM2C0SC (*(volatile char *)0x0065 )
#define TPM2C0V (*(volatile int *)0x0066 )
#define TPM2C0VH (*(volatile char *)0x0066 )
#define TPM2C0VL (*(volatile char *)0x0067 )
#define TPM2C1SC (*(volatile char *)0x0068 )
#define TPM2C1V (*(volatile int *)0x0069 )
#define TPM2C1VH (*(volatile char *)0x0069 )
#define TPM2C1VL (*(volatile char *)0x006A )
*/
//#endif /*defined(HEADER)*/
#endif /* defined(S08DZ60) */
/* Register definitions used in the driver sources */
/*IO register*/
#define LIN_PORTA PTAD /* port A */
#define LIN_PORTB PTBD /* port B */
#define LIN_DDRA PTADD /* data direction port A */
#define LIN_DDRB PTBDD /* data direction port B */
#define LIN_PORTP PTED /* port P */
#define LIN_DDRP PTEDD /* data direction port P */
//#define LIN_PTIP (*( (volatile LIN_BYTE*) &(LIN_Reg.ptip) )) /* input port P */
/*SCI register*/
#if defined SCI_1)
#define LIN_SCBDH SCI1BDH /* SCI 1 baud rate high */
#define LIN_SCBDL SCI1BDL /* SCI 1 baud rate low */
#define LIN_SCCR1 SCI1C1 /* SCI 1 control register 1 */
#define LIN_SCCR2 SCI1C2 /* SCI 1 control register 2 */
#define LIN_SCSR1 SCI1S1 /* SCI 1 status register 1 */
#define LIN_SCSR2 SCI1S2 /* SCI 1 status register 2 */
#define LIN_SCCR3 SCI1C3 /* SCI 1 control register 3 */
#define LIN_SCDR SCI1D /* SCI 1 data register */
#elif defined (SCI_2)
#define LIN_SCBDH SCI2BDH /* SCI 2 baud rate high */
#define LIN_SCBDL SCI2BDL /* SCI 2 baud rate low */
#define LIN_SCCR1 SCI2C1 /* SCI 2 control register 1 */
#define LIN_SCCR2 SCI2C2 /* SCI 2 control register 2 */
#define LIN_SCSR1 SCI2S1 /* SCI 2 status register 1 */
#define LIN_SCSR2 SCI2S2 /* SCI 2 status register 2 */
#define LIN_SCCR3 SCI2C3 /* SCI 2 control register 3 */
#define LIN_SCDR SCI2D /* SCI 2 data register */
#endif /*defined (SCI_1)*/
/*Timer register*/
#if defined TPM_1)
#define LIN_TPMSC TPM1SC
#define LIN_TPMCNT TPM1CNT
#define LIN_TPMCNTH TPM1CNTH
#define LIN_TPMCNTL TPM1CNTL
#define LIN_TPMMOD TPM1MOD
#define LIN_TPMMODH TPM1MODH
#define LIN_TPMMODL TPM1MODL
#if defined (CHANNEL_0)
#define LIN_TPMChanSC TPM1C0SC
#define LIN_TPMChanV TPM1C0V
#define LIN_TPMChanVH TPM1C0VH
#define LIN_TPMChanVL TPM1C0VL
#elif defined (CHANNEL_1)
#define LIN_TPMChanSC TPM1C1SC
#define LIN_TPMChanV TPM1C1V
#define LIN_TPMChanVH TPM1C1VH
#define LIN_TPMChanVL TPM1C1VL
#elif defined (CHANNEL_2)
#define LIN_TPMChanSC TPM1C2SC
#define LIN_TPMChanV TPM1C2V
#define LIN_TPMChanVH TPM1C2VH
#define LIN_TPMChanVL TPM1C2VL
#elif defined (CHANNEL_3)
#define LIN_TPMChanSC TPM1C3SC
#define LIN_TPMChanV TPM1C3V
#define LIN_TPMChanVH TPM1C3VH
#define LIN_TPMChanVL TPM1C3VL
#elif defined (CHANNEL_4)
#define LIN_TPMChanSC TPM1C4SC
#define LIN_TPMChanV TPM1C4V
#define LIN_TPMChanVH TPM1C4VH
#define LIN_TPMChanVL TPM1C4VL
#elif defined (CHANNEL_5)
#define LIN_TPMChanSC TPM1C5SC
#define LIN_TPMChanV TPM1C5V
#define LIN_TPMChanVH TPM1C5VH
#define LIN_TPMChanVL TPM1C5VL
#endif /*defined (CHANNEL_0)*/
#elif defined (TPM_2)
#define LIN_TPMSC TPM2SC
#define LIN_TPMCNT TPM2CNT
#define LIN_TPMCNTH TPM2CNTH
#define LIN_TPMCNTL TPM2CNTL
#define LIN_TPMMOD TPM2MOD
#define LIN_TPMMODH TPM2MODH
#define LIN_TPMMODL TPM2MODL
#if defined (CHANNEL_0)
#define LIN_TPMChanSC TPM2C0SC
#define LIN_TPMChanV TPM2C0V
#define LIN_TPMChanVH TPM2C0VH
#define LIN_TPMChanVL TPM2C0VL
#elif defined (CHANNEL_1)
#define LIN_TPMChanSC TPM2C1SC
#define LIN_TPMChanV TPM2C1V
#define LIN_TPMChanVH TPM2C1VH
#define LIN_TPMChanVL TPM2C1VL
#endif /*defined (CHANNEL_0)*/
#endif /*defined (TPM_1)*/
/******************* Bit masks *************************/
/* define bit mask for SCI */
#define LIN_SCCR1_LOOPS 0x80 /* Loop Mode/Single Wire Mode Enable in SCCR1 */
#define LIN_SCCR1_SCISWAI 0x40 /* SCI Stops in Wait Mode in SCCR1 */
#define LIN_SCCR1_RSRC 0x20 /* Receive source in SCCR1 */
#define LIN_SCCR1_M 0x10 /* Mode (character lenght) in SCCR1 */
#define LIN_SCCR1_WAKE 0x08 /* Wake-up by address Mark/Idle in SCCR1 */
#define LIN_SCCR1_ILT 0x04 /* Idle line type in SCCR1 */
#define LIN_SCCR1_PE 0x02 /* Parity Enable in SCCR1 */
#define LIN_SCCR1_PT 0x01 /* Parity bit in SCCR1 */
#define LIN_SCCR2_TIE 0x80 /* Transmit interrupt enable bit in SCCR2 */
#define LIN_SCCR2_TCIE 0x40 /* Transfer complited intrerrupt enable SCCR2 */
#define LIN_SCCR2_RIE 0x20 /* Reciver interrupt enable in SCCR2 */
#define LIN_SCCR2_ILIE 0x10 /* Idle line interrupt ebable in SCCR2 */
#define LIN_SCCR2_TE 0x08 /* Transmitter enable in SCCR2 */
#define LIN_SCCR2_RE 0x04 /* Receiver enable in SCCR2 */
#define LIN_SCCR2_RWU 0x02 /* Receiver wake-up in SCCR2 */
#define LIN_SCCR2_SBK 0x01 /* Send Break in SCCR2 */
#define LIN_SCSR1_TDRE 0x80 /* Transmit Data Register Empty Flag in SCSR1 */
#define LIN_SCSR1_TC 0x40 /* Transmit in SCSR1 */
#define LIN_SCSR1_RDRF 0x20 /* Receiver data register full flag in SCSR1 */
#define LIN_SCSR1_IDLE 0x10 /* Idle line detected flag in SCSR1 */
#define LIN_SCSR1_OR 0x08 /* Overrun error flag in SCSR1 */
#define LIN_SCSR1_NF 0x04 /* Noise error flag in SCSR1 */
#define LIN_SCSR1_FE 0x02 /* Framing error flag in SCSR1 */
#define LIN_SCSR1_PF 0x01 /* Parity error flag in SCSR1 */
#define LIN_SCSR2_RAF 0x01 /* Receiver Active Flag in SCSR2 */
#define LIN_SCSR2_BRK13 0x04 /* Break charachter Length in SCSR2 */
#define LIN_SCCR3_R8 0x80 /* Ninth Data Bit for Receiver in SCCR3 */
#define LIN_SCCR3_T8 0x40 /* Ninth Data Bit for Transmitter in SCCR3 */
#define LIN_SCCR3_TXDIR 0x20 /* TxD Pin Direction in Single-Wire ModeSCCR3 */
#define LIN_SCCR3_ORIE 0x08 /* Overrun Interrupt Enable in SCCR3 */
#define LIN_SCCR3_NEIE 0x04 /* Noise Error Interrupt Enable in SCCR3 */
#define LIN_SCCR3_FEIE 0x02 /* Framing Error Interrupt Enable in SCCR3 */
#define LIN_SCCR3_PEIE 0x01 /* Parity Error Interrupt Enable in SCCR3 */
/* general purpose I/O pins number */
#define LIN_PIN0 0x01
#define LIN_PIN1 0x02
#define LIN_PIN2 0x04
#define LIN_PIN3 0x08
#define LIN_PIN4 0x10
#define LIN_PIN5 0x20
#define LIN_PIN6 0x40
#define LIN_PIN7 0x80
/* bit masks for Timer Module (STM) */
#define LIN_TM_SC_PR 0x07 /* TPM Prescaler bits */
#define LIN_TM_SC_CLK 0x18 /* TPM Clock select bits */
#define LIN_TM_SC_CPWMS 0x20 /* Center-Aligned PWM Select */
#define LIN_TM_SC_TOIE 0x40 /* Overflow Interrupt Enable */
#define LIN_TM_SC_TOF 0x80 /* Overflow flag */
#define LIN_TM_ChanSC_ELSnA 0x04 /* Edge/Level Select Bit A */
#define LIN_TM_ChanSC_ELSnB 0x08 /* Edge/Level Select Bit B */
#define LIN_TM_ChanSC_MSnA 0x10 /* Mode Select A */
#define LIN_TM_ChanSC_MSnB 0x20 /* Mode Select B */
#define LIN_TM_ChanSC_CHnIE 0x40 /* Channel n Interrupt Enable */
#define LIN_TM_ChanSC_CHnF 0x80 /* Channel n Flag */
#endif /* define( S08 ) */
#endif /* !define (REGS_H) */
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