sfr_r823.h

瑞萨的DOME板LIN主从节点程序调试通过可以使用

/*------------------------------------------------------
  Timer RB secondary register
------------------------------------------------------*/
union	byte_def	trbsc_addr;
#define		trbsc		trbsc_addr.byte

/*------------------------------------------------------
  Timer RB Primary Register
------------------------------------------------------*/
union	byte_def	trbpr_addr;
#define		trbpr		trbpr_addr.byte

/*------------------------------------------------------
  Timer RE counter data register
------------------------------------------------------*/
union	byte_def	tresec_addr;
#define		tresec		tresec_addr.byte

/*------------------------------------------------------
  Timer RE compare data register
------------------------------------------------------*/
union	byte_def	tremin_addr;
#define		tremin		tremin_addr.byte

/*------------------------------------------------------
  Timer RE control register1
------------------------------------------------------*/
union	byte_def	trecr1_addr;
#define		trecr1		trecr1_addr.byte

#define		tcstf_trecr1	trecr1_addr.bit.b1		/* Timer RE count status flag */
#define		toena_trecr1	trecr1_addr.bit.b2		/* TREO pin output enable bit */
#define		int_trecr1		trecr1_addr.bit.b3		/* Interrupt request timing bit */
#define		trerst_trecr1	trecr1_addr.bit.b4		/* Timer RE reset bit */
#define		tstart_trecr1	trecr1_addr.bit.b7		/* Timer RE count start bit */

/*------------------------------------------------------
  Timer RE control register2
------------------------------------------------------*/
union	byte_def	trecr2_addr;
#define		trecr2		trecr2_addr.byte

#define		comie_trecr2	trecr2_addr.bit.b5		/* Compare match interrupt enable bit */

/*------------------------------------------------------
  Timer RE count source select register
------------------------------------------------------*/
union	byte_def	trecsr_addr;
#define		trecsr		trecsr_addr.byte

#define		rcs0_trecsr		trecsr_addr.bit.b0		/* Count source select bit */
#define		rcs1_trecsr		trecsr_addr.bit.b1		/* Count source select bit */
#define		rcs2_trecsr		trecsr_addr.bit.b2		/* 4-Bit counter select bit */
#define		rcs5_trecsr		trecsr_addr.bit.b5		/* Clock output select bit */
#define		rcs6_trecsr		trecsr_addr.bit.b6		/* Clock output select bit */

/*------------------------------------------------------
  Timer RD start register
------------------------------------------------------*/
union	byte_def	trdstr_addr;
#define		trdstr		trdstr_addr.byte

#define		tstart0_trdstr	trdstr_addr.bit.b0	/* TRD0 count start bit */
#define		tstart1_trdstr	trdstr_addr.bit.b1	/* TRD1 count start bit */
#define		csel0_trdstr	trdstr_addr.bit.b2	/* TRD0 count operation select bit */
#define		csel1_trdstr	trdstr_addr.bit.b3	/* TRD1 count operation select bit */

#define		tstop0_trdstr	csel0_trdstr
#define		tstop1_trdstr	csel1_trdstr

/*------------------------------------------------------
  Timer RD mode register
------------------------------------------------------*/
union	byte_def	trdmr_addr;
#define		trdmr		trdmr_addr.byte

#define		sync_trdmr		trdmr_addr.bit.b0	/* Timer RD synchronous bit */
#define		bfc0_trdmr		trdmr_addr.bit.b4	/* TRDGRC0 register function selection bit */
#define		bfd0_trdmr		trdmr_addr.bit.b5	/* TRDGRD0 register function selection bit */
#define		bfc1_trdmr		trdmr_addr.bit.b6	/* TRDGRC1 register function selection bit */
#define		bfd1_trdmr		trdmr_addr.bit.b7	/* TRDGRD1 register function selection bit */

#define		trdmdr			trdmr
#define		sync_trdmdr		sync_trdmr
#define		bfc0_trdmdr		bfc0_trdmr
#define		bfd0_trdmdr		bfd0_trdmr
#define		bfc1_trdmdr		bfc1_trdmr
#define		bfd1_trdmdr		bfd1_trdmr

/*------------------------------------------------------
  Timer RD PWM mode register
------------------------------------------------------*/
union	byte_def	trdpmr_addr;
#define		trdpmr		trdpmr_addr.byte

#define		pwmb0_trdpmr	trdpmr_addr.bit.b0	/* PWM mode of TRDIOB0 selection bit */
#define		pwmc0_trdpmr	trdpmr_addr.bit.b1	/* PWM mode of TRDIOC0 selection bit */
#define		pwmd0_trdpmr	trdpmr_addr.bit.b2	/* PWM mode of TRDIOD0 selection bit */
#define		pwmb1_trdpmr	trdpmr_addr.bit.b4	/* PWM mode of TRDIOB1 selection bit */
#define		pwmc1_trdpmr	trdpmr_addr.bit.b5	/* PWM mode of TRDIOC1 selection bit */
#define		pwmd1_trdpmr	trdpmr_addr.bit.b6	/* PWM mode of TRDIOD1 selection bit */

/*------------------------------------------------------
  Timer RD function control register
------------------------------------------------------*/
union	byte_def	trdfcr_addr;
#define		trdfcr			trdfcr_addr.byte

#define		cmd0_trdfcr		trdfcr_addr.bit.b0	/* Combination mode selection bit */
#define		cmd1_trdfcr		trdfcr_addr.bit.b1	/* Combination mode selection bit */
#define		ols0_trdfcr		trdfcr_addr.bit.b2	/* Normal-Phase output level selection bit */
#define		ols1_trdfcr		trdfcr_addr.bit.b3	/* Counter-Phase output level selection bit */
#define		adtrg_trdfcr	trdfcr_addr.bit.b4	/* A/D trigger enable bit */
#define		adeg_trdfcr		trdfcr_addr.bit.b5	/* A/D trigger edge selection bit */
#define		stclk_trdfcr	trdfcr_addr.bit.b6	/* External clock input selection bit */
#define		pwm3_trdfcr		trdfcr_addr.bit.b7	/* PWM3 mode selection bit */

/*------------------------------------------------------
  Timer RD output master enable register 1
------------------------------------------------------*/
union	byte_def	trdoer1_addr;
#define		trdoer1			trdoer1_addr.byte

#define		ea0_trdoer1		trdoer1_addr.bit.b0	/* TRDIOA0 output disable bit */
#define		eb0_trdoer1		trdoer1_addr.bit.b1	/* TRDIOB0 output disable bit */
#define		ec0_trdoer1		trdoer1_addr.bit.b2	/* TRDIOC0 output disable bit */
#define		ed0_trdoer1		trdoer1_addr.bit.b3	/* TRDIOD0 output disable bit */
#define		ea1_trdoer1		trdoer1_addr.bit.b4	/* TRDIOA1 output disable bit */
#define		eb1_trdoer1		trdoer1_addr.bit.b5	/* TRDIOB1 output disable bit */
#define		ec1_trdoer1		trdoer1_addr.bit.b6	/* TRDIOC1 output disable bit */
#define		ed1_trdoer1		trdoer1_addr.bit.b7	/* TRDIOD1 output disable bit */

/*------------------------------------------------------
  Timer RD output master enable register 2
------------------------------------------------------*/
union	byte_def	trdoer2_addr;
#define		trdoer2			trdoer2_addr.byte

#define		pto_trdoer2		trdoer2_addr.bit.b7	/* INT0 of pulse output forced cutoff signal input enabled bit */

/*------------------------------------------------------
  Timer RD output control register
------------------------------------------------------*/
union	byte_def	trdocr_addr;
#define		trdocr			trdocr_addr.byte

#define		toa0_trdocr		trdocr_addr.bit.b0	/* TRDIOA0 output level selection bit */
#define		tob0_trdocr		trdocr_addr.bit.b1	/* TRDIOB0 output level selection bit */
#define		toc0_trdocr		trdocr_addr.bit.b2	/* TRDIOC0 initial output level selection bit */
#define		tod0_trdocr		trdocr_addr.bit.b3	/* TRDIOD0 initial output level selection bit */
#define		toa1_trdocr		trdocr_addr.bit.b4	/* TRDIOA1 initial output level selection bit */
#define		tob1_trdocr		trdocr_addr.bit.b5	/* TRDIOB1 initial output level selection bit */
#define		toc1_trdocr		trdocr_addr.bit.b6	/* TRDIOC1 initial output level selection bit */
#define		tod1_trdocr		trdocr_addr.bit.b7	/* TRDIOD1 initial output level selection bit */

/*------------------------------------------------------
  Timer RD digital filter function selection register 0
------------------------------------------------------*/
union	byte_def	trddf0_addr;
#define		trddf0			trddf0_addr.byte

#define		dfa_trddf0		trddf0_addr.bit.b0	/* TRDIOA pin digital filter function selection bit */
#define		dfb_trddf0		trddf0_addr.bit.b1	/* TRDIOB pin digital filter function selection bit */
#define		dfc_trddf0		trddf0_addr.bit.b2	/* TRDIOC pin digital filter function selection bit */
#define		dfd_trddf0		trddf0_addr.bit.b3	/* TRDIOD pin digital filter function selection bit */
#define		dfck0_trddf0	trddf0_addr.bit.b6	/* Clock selection bit for digital filter function */
#define		dfck1_trddf0	trddf0_addr.bit.b7	/* Clock selection bit for digital filter function */

/*------------------------------------------------------
  Timer RD digital filter function selection register 1
------------------------------------------------------*/
union	byte_def	trddf1_addr;
#define		trddf1			trddf1_addr.byte

#define		dfa_trddf1		trddf1_addr.bit.b0	/* TRDIOA pin digital filter function selection bit */
#define		dfb_trddf1		trddf1_addr.bit.b1	/* TRDIOB pin digital filter function selection bit */
#define		dfc_trddf1		trddf1_addr.bit.b2	/* TRDIOC pin digital filter function selection bit */
#define		dfd_trddf1		trddf1_addr.bit.b3	/* TRDIOD pin digital filter function selection bit */
#define		dfck0_trddf1	trddf1_addr.bit.b6	/* Clock selection bit for digital filter function */
#define		dfck1_trddf1	trddf1_addr.bit.b7	/* Clock selection bit for digital filter function */

/*------------------------------------------------------
  Timer RD control register 0
------------------------------------------------------*/
union	byte_def	trdcr0_addr;
#define		trdcr0			trdcr0_addr.byte

#define		tck0_trdcr0		trdcr0_addr.bit.b0	/* Count source selection bit */
#define		tck1_trdcr0		trdcr0_addr.bit.b1	/* Count source selection bit */
#define		tck2_trdcr0		trdcr0_addr.bit.b2	/* Count source selection bit */
#define		tpsc0_trdcr0	tck0_trdcr0
#define		tpsc1_trdcr0	tck1_trdcr0
#define		tpsc2_trdcr0	tck2_trdcr0
#define		ckeg0_trdcr0	trdcr0_addr.bit.b3	/* External clock edge selection bit */
#define		ckeg1_trdcr0	trdcr0_addr.bit.b4	/* External clock edge selection bit */
#define		cclr0_trdcr0	trdcr0_addr.bit.b5	/* TRD0 counter clear selection bit */
#define		cclr1_trdcr0	trdcr0_addr.bit.b6	/* TRD0 counter clear selection bit */
#define		cclr2_trdcr0	trdcr0_addr.bit.b7	/* TRD0 counter clear selection bit */

/*------------------------------------------------------
  Timer RD control register 1
------------------------------------------------------*/
union	byte_def	trdcr1_addr;
#define		trdcr1			trdcr1_addr.byte

#define		tck0_trdcr1		trdcr1_addr.bit.b0	/* Count source selection bit */
#define		tck1_trdcr1		trdcr1_addr.bit.b1	/* Count source selection bit */
#define		tck2_trdcr1		trdcr1_addr.bit.b2	/* Count source selection bit */
#define		tpsc0_trdcr1	tck0_trdcr1
#define		tpsc1_trdcr1	tck1_trdcr1
#define		tpsc2_trdcr1	tck2_trdcr1
#define		ckeg0_trdcr1	trdcr1_addr.bit.b3	/* External clock edge selection bit */
#define		ckeg1_trdcr1	trdcr1_addr.bit.b4	/* External clock edge selection bit */
#define		cclr0_trdcr1	trdcr1_addr.bit.b5	/* TRD1 counter clear selection bit */
#define		cclr1_trdcr1	trdcr1_addr.bit.b6	/* TRD1 counter clear selection bit */
#define		cclr2_trdcr1	trdcr1_addr.bit.b7	/* TRD1 counter clear selection bit */

/*------------------------------------------------------
  Timer RD I/O control register A0
------------------------------------------------------*/
union	byte_def	trdiora0_addr;
#define		trdiora0		trdiora0_addr.byte

#define		ioa0_trdiora0	trdiora0_addr.bit.b0	/* TRDGRA control bit */
#define		ioa1_trdiora0	trdiora0_addr.bit.b1	/* TRDGRA control bit */
#define		ioa2_trdiora0	trdiora0_addr.bit.b2	/* TRDGRA mode selection bit */
#define		ioa3_trdiora0	trdiora0_addr.bit.b3	/* Input capture input switch bit */
#define		iob0_trdiora0	trdiora0_addr.bit.b4	/* TRDGRB control bit */
#define		iob1_trdiora0	trdiora0_addr.bit.b5	/* TRDGRB control bit */
#define		iob2_trdiora0	trdiora0_addr.bit.b6	/* TRDGRB mode selection bit */

/*------------------------------------------------------
  Timer RD I/O control register A1
------------------------------------------------------*/
union	byte_def	trdiora1_addr;
#define		trdiora1		trdiora1_addr.byte

#define		ioa0_trdiora1	trdiora1_addr.bit.b0	/* TRDGRA control bit */
#define		ioa1_trdiora1	trdiora1_addr.bit.b1	/* TRDGRA control bit */
#define		ioa2_trdiora1	trdiora1_addr.bit.b2	/* TRDGRA mode selection bit */
#define		ioa3_trdiora1	trdiora1_addr.bit.b3	/* Input capture input switch bit */
#define		iob0_trdiora1	trdiora1_addr.bit.b4	/* TRDGRB control bit */
#define		iob1_trdiora1	trdiora1_addr.bit.b5	/* TRDGRB control bit */
#define		iob2_trdiora1	trdiora1_addr.bit.b6	/* TRDGRB mode selection bit */

/*------------------------------------------------------
  Timer RD I/O control register C0
------------------------------------------------------*/
union	byte_def	trdiorc0_addr;
#define		trdiorc0		trdiorc0_addr.byte

#define		ioc0_trdiorc0	trdiorc0_addr.bit.b0	/* TRDGRC control bit */
#define		ioc1_trdiorc0	trdiorc0_addr.bit.b1	/* TRDGRC control bit */
#define		ioc2_trdiorc0	trdiorc0_addr.bit.b2	/* TRDGRC mode selection bit */
#define		ioc3_trdiorc0	trdiorc0_addr.bit.b3	/* TRDGRC register function selection bit */
#define		iod0_trdiorc0	trdiorc0_addr.bit.b4	/* TRDGRD control bit */
#define		iod1_trdiorc0	trdiorc0_addr.bit.b5	/* TRDGRD control bit */
#define		iod2_trdiorc0	trdiorc0_addr.bit.b6	/* TRDGRD mode selection bit */
#define		iod3_trdiorc0	trdiorc0_addr.bit.b7	/* TRDGRD register function selection bit */

/*------------------------------------------------------
  Timer RD I/O control register C1
------------------------------------------------------*/
union	byte_def	trdiorc1_addr;
#define		trdiorc1		trdiorc1_addr.byte

#define		ioc0_trdiorc1	trdiorc1_addr.bit.b0	/* TRDGRC control bit */
#define		ioc1_trdiorc1	trdiorc1_addr.bit.b1	/* TRDGRC control bit */
#define		ioc2_trdiorc1	trdiorc1_addr.bit.b2	/* TRDGRC mode selection bit */
#define		ioc3_trdiorc1	trdiorc1_addr.bit.b3	/* TRDGRC register function selection bit */
#define		iod0_trdiorc1	trdiorc1_addr.bit.b4	/* TRDGRD control bit */
#define		iod1_trdiorc1	trdiorc1_addr.bit.b5	/* TRDGRD control bit */
#define		iod2_trdiorc1	trdiorc1_addr.bit.b6	/* TRDGRD mode selection bit */
#define		iod3_trdiorc1	trdiorc1_addr.bit.b7	/* TRDGRD register function selection bit */

/*------------------------------------------------------
  Timer RD status register 0
------------------------------------------------------*/
union	byte_def	trdsr0_addr;
#define		trdsr0			trdsr0_addr.byte

#define		imfa_trdsr0		trdsr0_addr.bit.b0	/* Input capture / compare match flag A */
#define		imfb_trdsr0		trdsr0_addr.bit.b1	/* Input capture / compare match flag B */
#define		imfc_trdsr0		trdsr0_addr.bit.b2	/* Input capture / compare match flag C */
#define		imfd_trdsr0		trdsr0_addr.bit.b3	/* Input capture / compare match flag D */
#define		ovf_trdsr0		trdsr0_addr.bit.b4	/* Overflow flag */

/*------------------------------------------------------
  Timer RD status register 1
------------------------------------------------------*/
union	byte_def	trdsr1_addr;
#define		trdsr1			trdsr1_addr.byte

#define		imfa_trdsr1		trdsr1_addr.bit.b0	/* Input capture / compare match f