sfr_r823.h

瑞萨的DOME板LIN主从节点程序调试通过可以使用

#pragma	ADDRESS		trdgra1_addr	0158H	/* Timer RD general register A1 */

#pragma	ADDRESS		trdgrb1_addr	015AH	/* Timer RD general register B1 */

#pragma	ADDRESS		trdgrc1_addr	015CH	/* Timer RD general register C1 */

#pragma	ADDRESS		trdgrd1_addr	015EH	/* Timer RD general register D1 */

#pragma	ADDRESS		fmr4_addr		01B3H	/* Flash memory control register 4 */

#pragma	ADDRESS		fmr1_addr		01B5H	/* Flash memory control register 1 */

#pragma	ADDRESS		fmr0_addr		01B7H	/* Flash memory control register 0 */

#pragma ADDRESS     c0mctl          1300h       /* CAN0 message control register */

#pragma ADDRESS     c0mctl0         1300h       /* CAN0 message control register 0 */

#pragma ADDRESS     c0mctl1         1301h       /* CAN0 message control register 1 */

#pragma ADDRESS     c0mctl2         1302h       /* CAN0 message control register 2 */

#pragma ADDRESS     c0mctl3         1303h       /* CAN0 message control register 3 */

#pragma ADDRESS     c0mctl4         1304h       /* CAN0 message control register 4 */

#pragma ADDRESS     c0mctl5         1305h       /* CAN0 message control register 5 */

#pragma ADDRESS     c0mctl6         1306h       /* CAN0 message control register 6 */

#pragma ADDRESS     c0mctl7         1307h       /* CAN0 message control register 7 */

#pragma ADDRESS     c0mctl8         1308h       /* CAN0 message control register 8 */

#pragma ADDRESS     c0mctl9         1309h       /* CAN0 message control register 9 */

#pragma ADDRESS     c0mctl10        130ah       /* CAN0 message control register 10 */

#pragma ADDRESS     c0mctl11        130bh       /* CAN0 message control register 11 */

#pragma ADDRESS     c0mctl12        130ch       /* CAN0 message control register 12 */

#pragma ADDRESS     c0mctl13        130dh       /* CAN0 message control register 13 */

#pragma ADDRESS     c0mctl14        130eh       /* CAN0 message control register 14 */

#pragma ADDRESS     c0mctl15        130fh       /* CAN0 message control register 15 */

#pragma ADDRESS     c0ctlr_addr     1310h       /* CAN0 control register */

#pragma ADDRESS     c0str_addr      1312h       /* CAN0 status register */

#pragma ADDRESS     c0sstr_addr     1314h       /* CAN0 slot status register */

#pragma ADDRESS     c0icr_addr      1316h       /* CAN0 interrupt control register */

#pragma ADDRESS     c0idr_addr      1318h       /* CAN0 extended ID register */

#pragma ADDRESS     c0conr_addr     131ah       /* CAN0 configuration register */

#pragma ADDRESS     c0recr_addr     131ch       /* CAN0 receive error count register */

#pragma ADDRESS     c0tecr_addr     131dh       /* CAN0 transmit error count register */

#pragma ADDRESS     c0afs_addr      1342h       /* CAN0 acceptance filter support register */

#pragma ADDRESS     cclkr_addr      135fh       /* CAN0/1 clock select register */

#pragma ADDRESS     c0slot          1360h       /* CAN0 message box   :Message Object */

#pragma ADDRESS     c0slot0         1360h       /* CAN0 message box 0 :Message Object */

#pragma ADDRESS     c0slot1         1370h       /* CAN0 message box 1 :Message Object */

#pragma ADDRESS     c0slot2         1380h       /* CAN0 message box 2 :Message Object */

#pragma ADDRESS     c0slot3         1390h       /* CAN0 message box 3 :Message Object */

#pragma ADDRESS     c0slot4         13a0h       /* CAN0 message box 4 :Message Object */

#pragma ADDRESS     c0slot5         13b0h       /* CAN0 message box 5 :Message Object */

#pragma ADDRESS     c0slot6         13c0h       /* CAN0 message box 6 :Message Object */

#pragma ADDRESS     c0slot7         13d0h       /* CAN0 message box 7 :Message Object */

#pragma ADDRESS     c0slot8         13e0h       /* CAN0 message box 8 :Message Object */

#pragma ADDRESS     c0slot9         13f0h       /* CAN0 message box 9 :Message Object */

#pragma ADDRESS     c0slot10        1400h       /* CAN0 message box 10:Message Object */

#pragma ADDRESS     c0slot11        1410h       /* CAN0 message box 11:Message Object */

#pragma ADDRESS     c0slot12        1420h       /* CAN0 message box 12:Message Object */

#pragma ADDRESS     c0slot13        1430h       /* CAN0 message box 13:Message Object */

#pragma ADDRESS     c0slot14        1440h       /* CAN0 message box 14:Message Object */

#pragma ADDRESS     c0slot15        1450h       /* CAN0 message box 15:Message Object */

#pragma ADDRESS     c0gmr           1460h       /* CAN0 global mask register */

#pragma ADDRESS     c0lmar          1466h       /* CAN0 local mask A register */

#pragma ADDRESS     c0lmbr          146ch       /* CAN0 local mask B register */

/********************************************************
*  declare SFR bit                                      *
********************************************************/
struct	bit_def {
	char	b0:1;
	char	b1:1;
	char	b2:1;
	char	b3:1;
	char	b4:1;
	char	b5:1;
	char	b6:1;
	char	b7:1;
};
union	byte_def{
	struct	bit_def bit;
	char	byte;
};

/*------------------------------------------------------
  Processor mode register0
------------------------------------------------------*/
union	byte_def	pm0_addr;
#define		pm0			pm0_addr.byte

#define		pm03		pm0_addr.bit.b3			/* Software reset bit */

/*------------------------------------------------------
  Processor mode register1
------------------------------------------------------*/
union	byte_def	pm1_addr;
#define		pm1			pm1_addr.byte

#define		pm12		pm1_addr.bit.b2			/* WDT interrupt/reset switch bit */

/*------------------------------------------------------
  System clock control register0
------------------------------------------------------*/
union	byte_def	cm0_addr;
#define		cm0			cm0_addr.byte

#define		cm02		cm0_addr.bit.b2			/* WAIT peripheral function clock stop bit */
#define		cm05		cm0_addr.bit.b5			/* Xin clock (Xin-Xout) stop bit */
#define		cm06		cm0_addr.bit.b6			/* System clock division select bit0 */

/*------------------------------------------------------
  System clock control register1
------------------------------------------------------*/
union	byte_def	cm1_addr;
#define		cm1			cm1_addr.byte

#define		cm10		cm1_addr.bit.b0			/* All clock stop control bit */
#define		cm13		cm1_addr.bit.b3			/* Port Xin-Xout switch bit */
#define		cm14		cm1_addr.bit.b4			/* Low-speed on-chip oscillation stop bit */
#define		cm15		cm1_addr.bit.b5			/* Xin-Xout drive capacity select bit */
#define		cm16		cm1_addr.bit.b6			/* System clock division select bit1 */
#define		cm17		cm1_addr.bit.b7			/* System clock division select bit1 */

/*------------------------------------------------------
  Address match interrupt enable register
------------------------------------------------------*/
union	byte_def	aier_addr;
#define		aier		aier_addr.byte

#define		aier0		aier_addr.bit.b0		/* Address match interrupt 0 enable bit */
#define		aier1		aier_addr.bit.b1		/* Address match interrupt 1 enable bit */

/*------------------------------------------------------
  Protect register
------------------------------------------------------*/
union	byte_def	prcr_addr;
#define		prcr		prcr_addr.byte

#define		prc0		prcr_addr.bit.b0		/* Protect bit0 */
#define		prc1		prcr_addr.bit.b1		/* Protect bit1 */
#define		prc2		prcr_addr.bit.b2		/* Protect bit2 */
#define		prc3		prcr_addr.bit.b3		/* Protect bit3 */

/*------------------------------------------------------
  Oscillation stop detection register
------------------------------------------------------*/
union	byte_def	ocd_addr;
#define		ocd			ocd_addr.byte

#define		ocd0		ocd_addr.bit.b0			/* Oscillation stop detection enable bit */
#define		ocd1		ocd_addr.bit.b1			/* Oscillation stop detection interrupt enable bit */
#define		ocd2		ocd_addr.bit.b2			/* System clock select bit */
#define		ocd3		ocd_addr.bit.b3			/* Clock monitor bit */

/*------------------------------------------------------
  Watchdog timer reset register
------------------------------------------------------*/
union	byte_def	wdtr_addr;
#define		wdtr		wdtr_addr.byte

/*------------------------------------------------------
  Watchdog timer start register
------------------------------------------------------*/
union	byte_def	wdts_addr;
#define		wdts		wdts_addr.byte

/*------------------------------------------------------
  Watchdog timer control register
------------------------------------------------------*/
union	byte_def	wdc_addr;
#define		wdc			wdc_addr.byte

#define		wdc7		wdc_addr.bit.b7			/* Prescaler select bit */

/*------------------------------------------------------
  Count source protection mode register
------------------------------------------------------*/
union	byte_def	cspr_addr;
#define		cspr		cspr_addr.byte
#define		cspro		cspr_addr.bit.b7		/* Count source protection mode select bit */

/*------------------------------------------------------
  High-speed on-chip oscillator control register 0
------------------------------------------------------*/
union	byte_def	fra0_addr;
#define		fra0		fra0_addr.byte

#define		fra00		fra0_addr.bit.b0		/* High-speed on-chip oscillator enable bit */
#define		fra01		fra0_addr.bit.b1		/* High-speed on-chip oscillator select bit */

/*------------------------------------------------------
  High-speed on-chip oscillator control register 1
------------------------------------------------------*/
union	byte_def	fra1_addr;
#define		fra1		fra1_addr.byte

/*------------------------------------------------------
  High-speed on-chip oscillator control register 2
------------------------------------------------------*/
union	byte_def	fra2_addr;
#define		fra2		fra2_addr.byte

#define		fra20		fra2_addr.bit.b0		/* High-speed on-chip oscillator frequency switching bit */
#define		fra21		fra2_addr.bit.b1		/* High-speed on-chip oscillator frequency switching bit */
#define		fra22		fra2_addr.bit.b2		/* High-speed on-chip oscillator frequency switching bit */

/*------------------------------------------------------
  Voltage detection register 1
------------------------------------------------------*/
union	byte_def	vca1_addr;
#define		vca1		vca1_addr.byte

#define		vca13		vca1_addr.bit.b3		/* Voltage detection 2 signal monitor flag */

/*------------------------------------------------------
  Voltage detection register 2
------------------------------------------------------*/
union	byte_def	vca2_addr;
#define		vca2		vca2_addr.byte

#define		vca26		vca2_addr.bit.b6		/* Voltage detection 1 enable bit */
#define		vca27		vca2_addr.bit.b7		/* Voltage detection 2 enable bit */

/*------------------------------------------------------
  Voltage monitor 1 circuit control register
------------------------------------------------------*/
union	byte_def	vw1c_addr;
#define		vw1c		vw1c_addr.byte

#define		vw1c0		vw1c_addr.bit.b0		/* Voltage monitor 1 interrupt / reset enable bit */
#define		vw1c1		vw1c_addr.bit.b1		/* Voltage Monitor 1 digital filter disable mode select bit */
#define		vw1c2		vw1c_addr.bit.b2		/* Voltage change detection flag */
#define		vw1f0		vw1c_addr.bit.b4		/* Sampling clock select bit */
#define		vw1f1		vw1c_addr.bit.b5		/* Sampling clock select bit */
#define		vw1c6		vw1c_addr.bit.b6		/* Voltage monitor 1 circuit mode select bit */
#define		vw1c7		vw1c_addr.bit.b7		/* Voltage monitor 1 interrupt / reset generation condition select bit */

/*------------------------------------------------------
  Voltage monitor 2 circuit control register
------------------------------------------------------*/
union	byte_def	vw2c_addr;
#define		vw2c		vw2c_addr.byte

#define		vw2c0		vw2c_addr.bit.b0		/* Voltage monitor 2 interrupt / reset enable bit */
#define		vw2c1		vw2c_addr.bit.b1		/* Voltage monitor 2 digital filter disabled mode select bit */
#define		vw2c2		vw2c_addr.bit.b2		/* Voltage change detection flag */
#define		vw2c3		vw2c_addr.bit.b3		/* WDT Detection Flag */
#define		vw2f0		vw2c_addr.bit.b4		/* Sampling clock select bit */
#define		vw2f1		vw2c_addr.bit.b5		/* Sampling clock select bit */
#define		vw2c6		vw2c_addr.bit.b6		/* Voltage monitor 2 circuit mode select bit */
#define		vw2c7		vw2c_addr.bit.b7		/* Voltage monitor 2 interrupt / reset generation condition select bit */