green_tb.v

来自「This is an extension of sign example. Yo」· Verilog 代码 · 共 40 行

module green_tb;
wire [15:0]col1;
wire [15:0]scan1;
wire [4:0]count1;
reg clk1;
reg reset1;
parameter CLK = 50;
parameter DOUBLE_CLK = 100;
integer fp_scan,fp_col,fp_count;

green green1(.clk(clk1), .reset(reset1), .col(col1), .scan(scan1) , .count(count1));

//==========
initial
begin
	fp_scan = $fopen("scan.dat");
	fp_col = $fopen("col.dat");
	fp_count=$fopen("count.dat");	
	clk1 = 0;
	#250 reset1 = 1;
	#CLK reset1 = 0;	
	#80000	$finish;
end
//=========
always
begin
	#CLK clk1 =~clk1;
end
//========
always@(posedge clk1)
begin
	#CLK
	$fdisplay(fp_scan, scan1[15:0]);
	$fdisplay(fp_col, col1[15:0]);
	$fdisplay(fp_count, count1[4:0]);
end
endmodule