showfpga_tb.v

来自「As the source code name, this code is wr」· Verilog 代码 · 共 39 行

module showid_tb;
wire [7:0]col1;
wire [31:0]scan1;
reg clk1;
reg reset1;
reg up1;
parameter CLK = 50;
parameter DOUBLE_CLK = 100;
integer fp_scan,fp_col;
showid showFpga1(.clk(clk1), .reset(reset1), .col(col1), .scan(scan1), .up(up1));
//==========
initial
begin
	fp_scan = $fopen("scan.dat");
	fp_col = $fopen("col.dat");	
	clk1 = 0;
	up1=0;
	#250 reset1 = 1;
	#CLK reset1 = 0;	
	#50000 ;	
	#250 reset1 = 1;
	#CLK reset1 = 0;	
	#CLK up1=1;
	#90000 $finish;
end
//=========
always
begin
	#CLK  clk1 =~clk1;
end
//========
always@(posedge clk1)
begin
	#CLK $fdisplay(fp_scan, scan1[31:0]);
	     $fdisplay(fp_col, col1[7:0]);
end
endmodule