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📄 startup34.lst

📁 uPSD34xx Disk driver
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                     227     ;
                     228     ;  Reentrant Stack Initialization
                     229     ;
                     230     ;  The following EQU statements define the stack pointer for reentrant
                     231     ;  functions and initialized it:
                     232     ;
                     233     ;  Stack Space for reentrant functions in the SMALL model.
  0000               234     IBPSTACK        EQU     0       ; set to 1 if small reentrant is used.
  0100               235     IBPSTACKTOP     EQU     0FFH+1  ; set top of stack to highest location+1.
                     236     ;
                     237     ;  Stack Space for reentrant functions in the LARGE model.      
  0000               238     XBPSTACK        EQU     0       ; set to 1 if large reentrant is used.
  0000               239     XBPSTACKTOP     EQU     0FFFFH+1; set top of stack to highest location+1.
                     240     ;
                     241     ;  Stack Space for reentrant functions in the COMPACT model.    
  0000               242     PBPSTACK        EQU     0       ; set to 1 if compact reentrant is used.
  0000               243     PBPSTACKTOP     EQU     0FFFFH+1; set top of stack to highest location+1.
                     244     ;
                     245     ;------------------------------------------------------------------------------
                     246     ;
                     247     ;  Page Definition for Using the Compact Model with 64 KByte xdata RAM
                     248     ;
                     249     ;  The following EQU statements define the xdata page used for pdata
                     250     ;  variables. The EQU PPAGE must conform with the PPAGE control used
                     251     ;  in the linker invocation.
                     252     ;
  0000               253     PPAGEENABLE     EQU     0       ; set to 1 if pdata object are used.
                     254     ;
  0000               255     PPAGE           EQU     0       ; define PPAGE number.
                     256     ;
A51 MACRO ASSEMBLER  STARTUP34                                                            09/13/2005 18:00:20 PAGE     5

  00A0               257     PPAGE_SFR       DATA    0A0H    ; SFR that supplies uppermost address byte
                     258     ;               (most 8051 variants use P2 as uppermost address byte)
                     259     ;
                     260     ;------------------------------------------------------------------------------
                     261     
                     262     ; Standard SFR Symbols 
  00E0               263     ACC     DATA    0E0H
  00F0               264     B       DATA    0F0H
  0081               265     SP      DATA    81H
  0082               266     DPL     DATA    82H
  0083               267     DPH     DATA    83H
  009D               268     BUSCON  DATA    9DH
  00A8               269     IE      DATA    0A8H
                     270     
                     271     
                     272                     NAME    ?C_STARTUP
                     273     
                     274     
                     275     ?C_C51STARTUP   SEGMENT   CODE
                     276     ?STACK          SEGMENT   IDATA
                     277     
----                 278                     RSEG    ?STACK
0000                 279                     DS      1
                     280     
                     281                     EXTRN CODE (?C_START)
                     282                     PUBLIC  ?C_STARTUP
                     283     
----                 284                     CSEG    AT      0
0000 020000   F      285     ?C_STARTUP:     LJMP    STARTUP1    ; This is the POR reset vector
                     286     
                     287     ; Turbo Debug Interrupt Service routine - Do Not Remove
                     288     
----                 289                     CSEG    AT  063H    ; debug interrupt vector
0063 53CFFD          290                     ANL     0CFH,#0FDH  ; clear debug interrupt request flag
0066 00              291                     nop
0067 32              292                     RETI
                     293     
                     294     
                     295     
----                 296                     RSEG    ?C_C51STARTUP
0000                 297     STARTUP1:
                     298     
                     299     ; Turbo uPSD specific initialization - Set up BUSCON based on FREQ_OSC
                     300     
                     301     IF (1) > 0                        ; Check if a 5V or 3V Turbo uPSD device
                     302     
0000                 303     SETUP_BUSCON_5V:
                     304     IF (40000 ) > 24000                  ; PFQ CLK Frequence 25-40MHz   
0000 74C1            305                     MOV     A, #0C1H        ; Initialize the BUSCON register 
0002 F59D            306                     MOV     BUSCON, A       ; BUSCON.7 = 1, Prefetch Queue is Enabled 
                     307                                             ; BUSCON.6 = 1, Branch Cache is Enabled
                     308                                             ; BUSCON.5, BUSCON.4= 00B - 4 PFQCLK for Xdata Writ
                             e bus cycle
                     309                                             ; BUSCON.3, BUSCON.2= 00B - 4 PFQCLK for Xdata Read
                              bus cycle
                     310                                             ; BUSCON.1, BUSCON.0= 01B - 4 PFQCLK for Code Fetch
                              bus cycle
                     311     ELSE                                    ; PFQ CLK Frequence 8-24MHz 
                                             MOV     A, #0C0H        ; Initialize the BUSCON register 
                                             MOV     BUSCON, A       ; BUSCON.7 = 1, Prefetch Queue is Enabled 
                                                                     ; BUSCON.6 = 1, Branch Cache is Enabled
                                                                     ; BUSCON.5, BUSCON.4= 00B - 4 PFQCLK for Xdata Writ
                             e bus cycle
                                                                     ; BUSCON.3, BUSCON.2= 00B - 4 PFQCLK for Xdata Read
                              bus cycle
                                                                     ; BUSCON.1, BUSCON.0= 00B - 3 PFQCLK for Code Fetch
A51 MACRO ASSEMBLER  STARTUP34                                                            09/13/2005 18:00:20 PAGE     6

                              bus cycle
                             ENDIF
                     319     
                     320     ELSE 
                             SETUP_BUSCON_3V:
                             IF (40000 ) >  24000                 ; PFQ CLK Frequence 25-40MHz     
                                             MOV     A, #0D6H        ; Initialize the BUSCON register 
                                             MOV     BUSCON, A       ; BUSCON.7 = 1, Prefetch Queue is Enabled 
                                                                     ; BUSCON.6 = 1, Branch Cache is Enabled
                                                                     ; BUSCON.5, BUSCON.4= 01B - 5 PFQCLK for Xdata Writ
                             e bus cycle
                                                                     ; BUSCON.3, BUSCON.2= 01B - 5 PFQCLK for Xdata Read
                              bus cycle
                                                                     ; BUSCON.1, BUSCON.0= 10B - 5 PFQCLK for Code Fetch
                              bus cycle
                             ELSE                                    ; PFQ CLK Frequence 8-24MHz
                                             MOV     A, #0C0H        ; Initialize the BUSCON register 
                                             MOV     BUSCON, A       ; BUSCON.7 = 1, Prefetch Queue is Enabled 
                                                                     ; BUSCON.6 = 1, Branch Cache is Enabled
                                                                     ; BUSCON.5, BUSCON.4= 00B - 4 PFQCLK for Xdata Writ
                             e bus cycle
                                                                     ; BUSCON.3, BUSCON.2= 00B - 4 PFQCLK for Xdata Read
                              bus cycle
                                                                     ; BUSCON.1, BUSCON.0= 00B - 3 PFQCLK for Code Fetch
                              bus cycle
                             ENDIF
                             ENDIF
                     338     
                     339     
                     340     ; Other Turbo Init code goes here...
                     341     
0004 75A8C0          342                     MOV     IE, #0xC0       ; Enable Debug Interrupt
                     343     
                     344     IF IDATALEN <> 0
0007 78FF            345                     MOV     R0,#IDATALEN - 1
0009 E4              346                     CLR     A
000A F6              347     IDATALOOP:      MOV     @R0,A
000B D8FD            348                     DJNZ    R0,IDATALOOP
                     349     ENDIF
                     350     
                     351     IF XDATALEN <> 0
                                             MOV     DPTR,#XDATASTART
                                             MOV     R7,#LOW (XDATALEN)
                               IF (LOW (XDATALEN)) <> 0
                                             MOV     R6,#(HIGH (XDATALEN)) +1
                               ELSE
                                             MOV     R6,#HIGH (XDATALEN)
                               ENDIF
                                             CLR     A
                             XDATALOOP:      MOVX    @DPTR,A
                                             INC     DPTR
                                             DJNZ    R7,XDATALOOP
                                             DJNZ    R6,XDATALOOP
                             ENDIF
                     365     
                     366     IF PPAGEENABLE <> 0
                                             MOV     PPAGE_SFR,#PPAGE
                             ENDIF
                     369     
                     370     IF PDATALEN <> 0
                                             MOV     R0,#LOW (PDATASTART)
                                             MOV     R7,#LOW (PDATALEN)
                                             CLR     A
                             PDATALOOP:      MOVX    @R0,A
                                             INC     R0
                                             DJNZ    R7,PDATALOOP
A51 MACRO ASSEMBLER  STARTUP34                                                            09/13/2005 18:00:20 PAGE     7

                             ENDIF
                     378     
                     379     IF IBPSTACK <> 0
                             EXTRN DATA (?C_IBP)
                             
                                             MOV     ?C_IBP,#LOW IBPSTACKTOP
                             ENDIF
                     384     
                     385     IF XBPSTACK <> 0
                             EXTRN DATA (?C_XBP)
                             
                                             MOV     ?C_XBP,#HIGH XBPSTACKTOP
                                             MOV     ?C_XBP+1,#LOW XBPSTACKTOP
                             ENDIF
                     391     
                     392     IF PBPSTACK <> 0
                             EXTRN DATA (?C_PBP)
                                             MOV     ?C_PBP,#LOW PBPSTACKTOP
                             ENDIF
                     396     
000D 758100   F      397                     MOV     SP,#?STACK-1
                     398     ; This code is required if you use L51_BANK.A51 with Banking Mode 4
                     399     ; EXTRN CODE (?B_SWITCH0)
                     400     ;               CALL    ?B_SWITCH0      ; init bank mechanism to code bank 0
0010 020000   F      401                     LJMP    ?C_START
                     402     
                     403     
                     404     
                     405                     END
A51 MACRO ASSEMBLER  STARTUP34                                                            09/13/2005 18:00:20 PAGE     8

SYMBOL TABLE LISTING
------ ----- -------


N A M E             T Y P E  V A L U E   ATTRIBUTES

?C_C51STARTUP. . .  C SEG    0013H       REL=UNIT
?C_START . . . . .  C ADDR   -----       EXT
?C_STARTUP . . . .  C ADDR   0000H   A   
?STACK . . . . . .  I SEG    0001H       REL=UNIT
ACC. . . . . . . .  D ADDR   00E0H   A   
B. . . . . . . . .  D ADDR   00F0H   A   
BUSCON . . . . . .  D ADDR   009DH   A   
DPH. . . . . . . .  D ADDR   0083H   A   
DPL. . . . . . . .  D ADDR   0082H   A   
IBPSTACK . . . . .  N NUMB   0000H   A   
IBPSTACKTOP. . . .  N NUMB   0100H   A   
IDATALEN . . . . .  N NUMB   0100H   A   
IDATALOOP. . . . .  C ADDR   000AH   R   SEG=?C_C51STARTUP
IE . . . . . . . .  D ADDR   00A8H   A   
PBPSTACK . . . . .  N NUMB   0000H   A   
PBPSTACKTOP. . . .  N NUMB   0000H   A   
PDATALEN . . . . .  N NUMB   0000H   A   
PDATASTART . . . .  N NUMB   0000H   A   
PPAGE. . . . . . .  N NUMB   0000H   A   
PPAGEENABLE. . . .  N NUMB   0000H   A   
PPAGE_SFR. . . . .  D ADDR   00A0H   A   
SETUP_BUSCON_5V. .  C ADDR   0000H   R   SEG=?C_C51STARTUP
SP . . . . . . . .  D ADDR   0081H   A   
STARTUP1 . . . . .  C ADDR   0000H   R   SEG=?C_C51STARTUP
XBPSTACK . . . . .  N NUMB   0000H   A   
XBPSTACKTOP. . . .  N NUMB   0000H   A   
XDATALEN . . . . .  N NUMB   0000H   A   
XDATASTART . . . .  N NUMB   0000H   A   


REGISTER BANK(S) USED: 0 

ASSEMBLY COMPLETE.  0 WARNING(S), 0 ERROR(S)

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