📄 msp430xe42x.h
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DEFC( SD16INCTL2 , SD16INCTL2_)
#define SD16PRE0_ (0x00B8) /* SD16 Preload Register Channel 0 */
DEFC( SD16PRE0 , SD16PRE0_)
#define SD16PRE1_ (0x00B9) /* SD16 Preload Register Channel 1 */
DEFC( SD16PRE1 , SD16PRE1_)
#define SD16PRE2_ (0x00BA) /* SD16 Preload Register Channel 2 */
DEFC( SD16PRE2 , SD16PRE2_)
#define SD16CONF0_ (0x00B7) /* SD16 Internal Configuration Register 0 */
DEFC( SD16CONF0 , SD16CONF0_)
#define SD16CONF1_ (0x00BF) /* SD16 Internal Configuration Register 1 */
DEFC( SD16CONF1 , SD16CONF1_)
/* Please use only the recommended settings */
#define SD16CTL_ (0x0100) /* Sigma Delta ADC 16 Control Register */
DEFW( SD16CTL , SD16CTL_)
#define SD16CCTL0_ (0x0102) /* SD16 Channel 0 Control Register */
DEFW( SD16CCTL0 , SD16CCTL0_)
#define SD16CCTL1_ (0x0104) /* SD16 Channel 1 Control Register */
DEFW( SD16CCTL1 , SD16CCTL1_)
#define SD16CCTL2_ (0x0106) /* SD16 Channel 2 Control Register */
DEFW( SD16CCTL2 , SD16CCTL2_)
#define SD16IV_ (0x0110) /* SD16 Interrupt Vector Register */
DEFW( SD16IV , SD16IV_)
#define SD16MEM0_ (0x0112) /* SD16 Channel 0 Conversion Memory */
DEFW( SD16MEM0 , SD16MEM0_)
#define SD16MEM1_ (0x0114) /* SD16 Channel 1 Conversion Memory */
DEFW( SD16MEM1 , SD16MEM1_)
#define SD16MEM2_ (0x0116) /* SD16 Channel 2 Conversion Memory */
DEFW( SD16MEM2 , SD16MEM2_)
/* SD16INCTLx - AFEINCTLx */
#define SD16INCH0 (0x0001) /* SD16 Input Channel select 0 */
#define SD16INCH1 (0x0002) /* SD16 Input Channel select 1 */
#define SD16INCH2 (0x0004) /* SD16 Input Channel select 2 */
#define SD16GAIN0 (0x0008) /* SD16 Input Pre-Amplifier Gain Select 0 */
#define SD16GAIN1 (0x0010) /* SD16 Input Pre-Amplifier Gain Select 1 */
#define SD16GAIN2 (0x0020) /* SD16 Input Pre-Amplifier Gain Select 2 */
#define SD16INTDLY0 (0x0040) /* SD16 Interrupt Delay after 1.Conversion 0 */
#define SD16INTDLY1 (0x0080) /* SD16 Interrupt Delay after 1.Conversion 1 */
#define SD16GAIN_1 (0x0000) /* SD16 Input Pre-Amplifier Gain Select *1 */
#define SD16GAIN_2 (0x0008) /* SD16 Input Pre-Amplifier Gain Select *2 */
#define SD16GAIN_4 (0x0010) /* SD16 Input Pre-Amplifier Gain Select *4 */
#define SD16GAIN_8 (0x0018) /* SD16 Input Pre-Amplifier Gain Select *8 */
#define SD16GAIN_16 (0x0020) /* SD16 Input Pre-Amplifier Gain Select *16 */
#define SD16GAIN_32 (0x0028) /* SD16 Input Pre-Amplifier Gain Select *32 */
#define SD16INCH_0 (0x0000) /* SD16 Input Channel select input */
#define SD16INCH_1 (0x0001) /* SD16 Input Channel select input */
#define SD16INCH_2 (0x0002) /* SD16 Input Channel select input */
#define SD16INCH_3 (0x0003) /* SD16 Input Channel select input */
#define SD16INCH_4 (0x0004) /* SD16 Input Channel select input */
#define SD16INCH_5 (0x0005) /* SD16 Input Channel select input */
#define SD16INCH_6 (0x0006) /* SD16 Input Channel select Temp */
#define SD16INCH_7 (0x0007) /* SD16 Input Channel select Offset */
#define SD16INTDLY_0 (0x0000) /* SD16 Interrupt Delay: Int. after 4.Conversion */
#define SD16INTDLY_1 (0x0040) /* SD16 Interrupt Delay: Int. after 3.Conversion */
#define SD16INTDLY_2 (0x0080) /* SD16 Interrupt Delay: Int. after 2.Conversion */
#define SD16INTDLY_3 (0x00C0) /* SD16 Interrupt Delay: Int. after 1.Conversion */
/* SD16CTL - AFECTL */
#define SD16OVIE (0x0002) /* SD16 Overflow Interupt Enable */
#define SD16REFON (0x0004) /* SD16 Switch internal Reference on */
#define SD16VMIDON (0x0008) /* SD16 Switch Vmid Buffer on */
#define SD16SSEL0 (0x0010) /* SD16 Clock Source Select 0 */
#define SD16SSEL1 (0x0020) /* SD16 Clock Source Select 1 */
#define SD16DIV0 (0x0040) /* SD16 Clock Divider Select 0 */
#define SD16DIV1 (0x0080) /* SD16 Clock Divider Select 1 */
#define SD16LP (0x0100) /* SD16 Low Power Mode Enable */
#define SD16DIV_0 (0x0000) /* SD16 Clock Divider Select /1 */
#define SD16DIV_1 (SD16DIV0) /* SD16 Clock Divider Select /2 */
#define SD16DIV_2 (SD16DIV1) /* SD16 Clock Divider Select /4 */
#define SD16DIV_3 (SD16DIV0+SD16DIV1) /* SD16 Clock Divider Select /8 */
#define SD16SSEL_0 (0x0000) /* SD16 Clock Source Select MCLK */
#define SD16SSEL_1 (SD16SSEL0) /* SD16 Clock Source Select SMCLK */
#define SD16SSEL_2 (SD16SSEL1) /* SD16 Clock Source Select ACLK */
#define SD16SSEL_3 (SD16SSEL0+SD16SSEL1) /* SD16 Clock Source Select TACLK */
/* SD16CCTLx - AFECCTLx */
#define SD16GRP (0x0001) /* SD16 Grouping of Channels: 0:Off/1:On */
#define SD16SC (0x0002) /* SD16 Start Conversion */
#define SD16IFG (0x0004) /* SD16 Channel x Interrupt Flag */
#define SD16IE (0x0008) /* SD16 Channel x Interrupt Enable */
#define SD16DF (0x0010) /* SD16 Channel x Data Format: 0:Unipolar/1:Bipolar */
#define SD16OVIFG (0x0020) /* SD16 Channel x Overflow Interrupt Flag */
#define SD16LSBACC (0x0040) /* SD16 Channel x Access LSB of ADC */
#define SD16LSBTOG (0x0080) /* SD16 Channel x Toggle LSB Output of ADC */
#define SD16OSR0 (0x0100) /* SD16 Channel x OverSampling Ratio 0 */
#define SD16OSR1 (0x0200) /* SD16 Channel x OverSampling Ratio 1 */
#define SD16SNGL (0x0400) /* SD16 Channel x Single Conversion On/Off */
#define SD16OSR_256 (0x0000) /* SD16 Channel x OverSampling Ratio 256 */
#define SD16OSR_128 (0x0100) /* SD16 Channel x OverSampling Ratio 128 */
#define SD16OSR_64 (0x0200) /* SD16 Channel x OverSampling Ratio 64 */
#define SD16OSR_32 (0x0300) /* SD16 Channel x OverSampling Ratio 32 */
/************************************************************
* ESP430E
************************************************************/
#define __MSP430_HAS_ESP430E__ /* Definition to show that Module is available */
#define AFEINCTL0 SD16INCTL0 /* AFE Input Control Register Channel 0 */
#define AFEINCTL1 SD16INCTL1 /* AFE Input Control Register Channel 1 */
#define AFEINCTL2 SD16INCTL2 /* AFE Input Control Register Channel 2 */
#define AFECTL SD16CTL /* Analog Front End Control Register */
#define AFECCTL0 SD16CCTL0 /* AFE Channel 0 Control Register */
#define AFECCTL1 SD16CCTL1 /* AFE Channel 1 Control Register */
#define AFECCTL2 SD16CCTL2 /* AFE Channel 2 Control Register */
#define ESPCTL_ (0x0150) /* ESP430 Control Register */
DEFW( ESPCTL , ESPCTL_)
#define MBCTL_ (0x0152) /* Mailbox Control Register */
DEFW( MBCTL , MBCTL_)
#define MBIN0_ (0x0154) /* Incoming Mailbox 0 Register */
DEFW( MBIN0 , MBIN0_)
#define MBIN1_ (0x0156) /* Incoming Mailbox 1 Register */
DEFW( MBIN1 , MBIN1_)
#define MBOUT0_ (0x0158) /* Outgoing Mailbox 0 Register */
DEFW( MBOUT0 , MBOUT0_)
#define MBOUT1_ (0x015A) /* Outgoing Mailbox 1 Register */
DEFW( MBOUT1 , MBOUT1_)
#define ESP430_STAT0_ (0x01C0) /* ESP430 Return Value 0 */
READ_ONLY DEFW( ESP430_STAT0 , ESP430_STAT0_)
#define ESP430_STAT1_ (0x01C2) /* ESP430 Return Value 1 */
READ_ONLY DEFW( ESP430_STAT1 , ESP430_STAT1_)
#define WAVEFSV1_ (0x01C4) /* ESP430 Return Value 2 */
READ_ONLY DEFW( WAVEFSV1 , WAVEFSV1_)
#define RET3_ (0x01C6) /* ESP430 Return Value 3 */
READ_ONLY DEFW( RET3 , RET3_)
#define RET4_ (0x01C8) /* ESP430 Return Value 4 */
READ_ONLY DEFW( RET4 , RET4_)
#define WAVEFSI1_ (0x01CA) /* ESP430 Return Value 5 */
READ_ONLY DEFW( WAVEFSI1 , WAVEFSI1_)
#define WAVEFSI2_ (0x01CC) /* ESP430 Return Value 6 */
READ_ONLY DEFW( WAVEFSI2 , WAVEFSI2_)
#define RET7_ (0x01CE) /* ESP430 Return Value 7 */
READ_ONLY DEFW( RET7 , RET7_)
#define ACTENERGY1_LO_ (0x01D0) /* ESP430 Return Value 8 */
READ_ONLY DEFW( ACTENERGY1_LO , ACTENERGY1_LO_)
#define ACTENERGY1_HI_ (0x01D2) /* ESP430 Return Value 9 */
READ_ONLY DEFW( ACTENERGY1_HI , ACTENERGY1_HI_)
#define ACTENERGY2_LO_ (0x01D4) /* ESP430 Return Value 10 */
READ_ONLY DEFW( ACTENERGY2_LO , ACTENERGY2_LO_)
#define ACTENERGY2_HI_ (0x01D6) /* ESP430 Return Value 11 */
READ_ONLY DEFW( ACTENERGY2_HI , ACTENERGY2_HI_)
#define REACTENERGY_LO_ (0x01D8) /* ESP430 Return Value 12 */
READ_ONLY DEFW( REACTENERGY_LO , REACTENERGY_LO_)
#define REACTENERGY_HI_ (0x01DA) /* ESP430 Return Value 13 */
READ_ONLY DEFW( REACTENERGY_HI , REACTENERGY_HI_)
#define APPENERGY_LO_ (0x01DC) /* ESP430 Return Value 14 */
READ_ONLY DEFW( APPENERGY_LO , APPENERGY_LO_)
#define APPENERGY_HI_ (0x01DE) /* ESP430 Return Value 15 */
READ_ONLY DEFW( APPENERGY_HI , APPENERGY_HI_)
#define ACTENSPER1_LO_ (0x01E0) /* ESP430 Return Value 16 */
READ_ONLY DEFW( ACTENSPER1_LO , ACTENSPER1_LO_)
#define ACTENSPER1_HI_ (0x01E2) /* ESP430 Return Value 17 */
READ_ONLY DEFW( ACTENSPER1_HI , ACTENSPER1_HI_)
#define ACTENSPER2_LO_ (0x01E4) /* ESP430 Return Value 18 */
READ_ONLY DEFW( ACTENSPER2_LO , ACTENSPER2_LO_)
#define ACTENSPER2_HI_ (0x01E6) /* ESP430 Return Value 19 */
READ_ONLY DEFW( ACTENSPER2_HI , ACTENSPER2_HI_)
#define POWERFCT_ (0x01E8) /* ESP430 Return Value 20 */
READ_ONLY DEFW( POWERFCT , POWERFCT_)
#define CAPIND_ (0x01EA) /* ESP430 Return Value 21 */
READ_ONLY DEFW( CAPIND , CAPIND_)
#define MAINSPERIOD_ (0x01EC) /* ESP430 Return Value 22 */
READ_ONLY DEFW( MAINSPERIOD , MAINSPERIOD_)
#define V1RMS_ (0x01EE) /* ESP430 Return Value 23 */
READ_ONLY DEFW( V1RMS , V1RMS_)
#define IRMS_LO_ (0x01F0) /* ESP430 Return Value 24 */
READ_ONLY DEFW( IRMS_LO , IRMS_LO_)
#define IRMS_HI_ (0x01F2) /* ESP430 Return Value 25 */
READ_ONLY DEFW( IRMS_HI , IRMS_HI_)
#define VPEAK_ (0x01F4) /* ESP430 Return Value 26 */
READ_ONLY DEFW( VPEAK , VPEAK_)
#define IPEAK_ (0x01F6) /* ESP430 Return Value 27 */
READ_ONLY DEFW( IPEAK , IPEAK_)
#define LINECYCLCNT_LO_ (0x01F8) /* ESP430 Return Value 28 */
READ_ONLY DEFW( LINECYCLCNT_LO , LINECYCLCNT_LO_)
#define LINECYCLCNT_HI_ (0x01FA) /* ESP430 Return Value 29 */
READ_ONLY DEFW( LINECYCLCNT_HI , LINECYCLCNT_HI_)
#define NMBMEAS_LO_ (0x01FC) /* ESP430 Return Value 30 */
READ_ONLY DEFW( NMBMEAS_LO , NMBMEAS_LO_)
#define NMBMEAS_HI_ (0x01FE) /* ESP430 Return Value 31 */
READ_ONLY DEFW( NMBMEAS_HI , NMBMEAS_HI_)
#define RET0 ESP430_STAT0 /* STATUS0 of ESP430 */
#define RET1 ESP430_STAT1 /* STATUS1 of ESP430 */
#define RET2 WAVEFSV1 /* Waveform Sample V1 offset corrected*/
#define RET5 WAVEFSI1 /* Waveform Sample I1 offset corrected*/
#define RET6 WAVEFSI2 /* Waveform Sample I2 offset corrected*/
#define RET8 ACTENERGY1_LO /* Active energy I1 Low Word */
#define RET9 ACTENERGY1_HI /* Active energy I1 High Word */
#define RET10 ACTENERGY2_LO /* Active energy I2 Low Word */
#define RET11 ACTENERGY2_HI /* Active energy I2 High Word*/
#define RET12 REACTENERGY_LO /* Reactive energy Low Word */
#define RET13 REACTENERGY_HI /* Reactive energy High Word */
#define RET14 APPENERGY_LO /* Apparent energy Low Word */
#define RET15 APPENERGY_HI /* Apparent energy High Word */
#define RET16 ACTENSPER1_LO /* Active energy I1 for last mains period Low Word */
#define RET17 ACTENSPER1_HI /* Active energy I1 for last mains period High Word */
#define RET18 ACTENSPER2_LO /* Active energy I2 for last mains period Low Word */
#define RET19 ACTENSPER2_HI /* Active energy I2 for last mains period High Word */
#define RET20 POWERFCT /* Power factor */
#define RET21 CAPIND /* Power factor: neg: inductive pos: cap. (LowByte)*/
#define RET22 MAINSPERIOD /* Mains period */
#define RET23 V1RMS /* Voltage RMS V1 value last second */
#define RET24 IRMS_LO /* Current RMS value last second I1 I2 Low Word */
#define RET25 IRMS_HI /* Current RMS value last second I1 I2 High Word */
#define RET26 VPEAK /* Voltage V1 absolute peak value */
#define RET27 IPEAK /* Current absolute peak value I1 I2 */
#define RET28 LINECYCLCNT_LO /* Line cycle counter Low Word */
#define RET29 LINECYCLCNT_HI /* Line cycle counter High Word */
#define RET30 NMBMEAS_LO /* Number of Measurements for CPU signal Low Word */
#define RET31 NMBMEAS_HI /* Number of Measurements for CPU signal High Word */
/* ESPCTL */
#define ESPEN (0x0001) /* ESP430 Module enable */
#define ESPSUSP (0x0002) /* ESP430 Module suspend */
#define IREQ (0x0004) /* NOT supported by current ESP430 Software */
/* RET0 - Status0 Flags */
#define WFSRDYFG (0x0001) /* New waveform Samples ready Flag */
#define I2GTI1FG (0x0002) /* Current I2 greater then I1 Flag */
#define ILREACHEDFG (0x0004) /* Interrupt level reached Flag */
#define ENRDYFG (0x0008) /* New Energy values ready Flag */
#define ZXLDFG (0x0010) /* Zero Crossing of V1 Flag (leading edge) */
#define ZXTRFG (0x0020) /* Zero Crossing of V1 Flag (trailing edge) */
#define CALRDYFG (0x0040) /* Calibration values ready Flag */
#define TAMPFG (0x0080) /* Tampering Occured Flag */
#define NEGENFG (0x0100) /* Negativ Energy Flag */
#define VDROPFG (0x0200) /* Voltage drop occured Flag */
#define VPEAKFG (0x0400) /* Voltage exceed VPeak level Flag */
#define I1PEAKFG (0x0800) /* Current exceed I1Peak level Flag */
#define I2PEAKFG (0x1000) /* Current exceed I2Peak level Flag */
//#define RESERVED (0x8000) /* Reserved */
//#define RESERVED (0x8000) /* Reserved */
#define ACTIVEFG (0x8000) /* Measurement or Calibration running Flag */
/* MBCTL */
#define IN0IFG (0x0001) /* Incoming Mail 0 Interrupt Flag */
#define IN1IFG (0x0002) /* Incoming Mail 1 Interrupt Flag */
#define OUT0FG (0x0004) /* Outgoing Mail 0 Flag */
#define OUT1FG (0x0008) /* Outgoing Mail 1 Flag */
#define IN0IE (0x0010) /* Incoming Mail 0 Interrupt Enable */
#define IN1IE (0x0020) /* Incoming Mail 1 Interrupt Enable */
#define CLR0OFF (0x0040) /* Switch off automatic clear of IN0IFG */
#define CLR1OFF (0x0080) /* Switch off automatic clear of IN1IFG */
#define OUT0IFG (0x0100) /* Outgoing Mail 0 Interrupt Flag */
#define OUT1IFG (0x0200) /* Outgoing Mail 1 Interrupt Flag */
#define OUT0IE (0x0400) /* Outgoing Mail 0 Interrupt Enable */
#define OUT1IE (0x0800) /* Outgoing Mail 1 Interrupt Enable */
/* Messages to ESP */
#define mRESET (0x0001) /* Restart ESP430 Software */
#define mSET_MODE (0x0003) /* Set Operation Mode for ESP430 Software */
#define mCLR_EVENT (0x0005) /* Clear Flags for ESP430 Software */
#define mINIT (0x0007) /* Initialize ESP430 Software */
#define mTEMP (0x0009) /* Request Temp. Measurement from ESP430 Software */
#define mSWVERSION (0x000B) /* Request software version of ESP430 */
#define mREAD_PARAM (0x000D) /* Request to read the parameter with no. 揚arameter No.⌨️ 快捷键说明
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