oscope.v

来自「Abstract A new intelligent milometer b」· Verilog 代码 · 共 56 行

// Copyright (c) Charles HY Cheung, Cornell University
//oscope (interface to trace buffer)
/*writes to RAM until triggered or held*/

module OSCOPE (
input reset,
input hold,
input trigger_enable,
input [15:0] threshold,
input threshold_posedge,
input writeclk,
input selectclk,
input inputclk,
input [15:0] inputdata,
input [15:0] max_samps,
output data_full,
//RAM
output	ram_we,
output reg [15:0] ram_data,
output reg [15:0] ram_addr
	);

wire stop, trigger;
reg threshold1, threshold2;

assign stop = (hold | (trigger & trigger_enable));
//we only when not stopped
assign ram_we = ~stop;
assign data_full = ram_addr[15] | (ram_addr == max_samps);

wire internalclk = (selectclk) ? inputclk : writeclk;

//save data
always @ (posedge internalclk or posedge reset)
begin
if (reset) 
	begin
	ram_data <= 16'd0;
	ram_addr <= 16'd0;
	end
else if (~stop)
	begin
	ram_data <= inputdata;
	ram_addr <= (ram_addr == max_samps)? 16'd0 : (ram_addr + 16'd1); //shift address only when not stopped
	end
end

//trigger threshold detect
always @(posedge internalclk) threshold1 <= ( threshold_posedge ~^ (ram_data>=threshold) );

//save prev value
always @(posedge internalclk) threshold2 <= threshold1;
assign trigger = threshold1 & ~threshold2;  // trigger on edge

endmodule