📄 amplifier.v
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// Copyright (c) Charles HY Cheung, Cornell University
/*`Data is read on positive clk edge*/
/* ampin * gain = ampout*/
/*amplifier based on gain factor*320mV*/
/*output is 16-bit 2s comp (c000-FFFF, 0000-4000)*/
module AMPLIFIER(gain, ampin, ampout);
input signed [17:0] gain; /*gain factor from -320mV to 320mV*/
input [15:0] ampin; /*16-bit input*/
output [15:0] ampout; /*16-bit output*/
wire signed [17:0] outputdata;
assign ampout = outputdata[15:0];
//apply gain
signed_mult ampmult0 (outputdata,{ampin[15],ampin[15],ampin}, gain);
endmodule
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