deltasigma.v

来自「Abstract A new intelligent milometer b」· Verilog 代码 · 共 56 行

// Copyright (c) Charles HY Cheung, Cornell University
/*1st order digital Delta-Sigma modulator*/
/*`Data is read on positive clk edge*/
module DELTASIGMA(clk, reset, analogin, bitstream);

input clk; /*clock - max 20 mhz*/ 
input reset;
input [15:0] analogin; /*2's complement word from amplifier - range from: -320mV to 320mV*/

output bitstream; /*16-bit clocked 1-bit stream*/

wire signed [17:0] diff1;//, diff2;/*output of difference*/
reg [15:0] ddc_out; /*output of DDC*/
reg	signed [17:0] add1;//, add2; /*adder clocked (latched) output*/
//reg [1:0] bitcount;

/*BITSTREAM (adder output MSB)*/
assign bitstream = add1[17]; //most significant bit of adder output
/*1-bit DDC*/
//assign ddc_out = bitstream ? 16'h4000 : 16'hC000;
/*DIFFERENCE (impulse FEEDBACK)*/
assign diff1 = {analogin[15], analogin[15], analogin} - {ddc_out[15], ddc_out[15], ddc_out};
//assign diff2 = add1 - {2'd0, ddc_out[15], ddc_out[15],16'd0, ddc_out};




/*ADDER - latched to pos clk*/
always @ (posedge clk or posedge reset)
begin
if (reset)
	begin
		add1 <= 36'h0;
		//add2 <= 36'h0;
	end
else
	begin
		add1 <= diff1 + add1;
		//add2 <= diff2 + add2;
	end
end
/*
always @ (posedge clk or posedge reset)
begin
if (reset) bitcount <= 2'd0;
else bitcount <= bitcount + 1;
end
*/
/*DDC*/
always @ (posedge clk or posedge reset)
begin
if (reset) ddc_out <= 16'h0;
else ddc_out <= bitstream ? 16'h4000 : 16'hC000;
end

endmodule