dmac.h

realtek562x系列驱动源码。wince

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/*++

$Workfile: DMAC.h $

$Date: 12/23/04 4:47a $

Abstract:  
      The PDD (Platform Dependent Driver) is responsible for
      communicating with the audio circuit to start and stop playback
      and/or recording and initialize and deinitialize the circuits.

      This driver is specifically written for the UCB 1400 Audio Codec.

	    
Notes: 

/* 
** Copyright 2000-2003 Intel Corporation All Rights Reserved.
**
** Portions of the source code contained or described herein and all documents
** related to such source code (Material) are owned by Intel Corporation
** or its suppliers or licensors and is licensed by Microsoft Corporation for distribution.  
** Title to the Material remains with Intel Corporation or its suppliers and licensors. 
** Use of the Materials is subject to the terms of the Microsoft license agreement which accompanied the Materials.  
** No other license under any patent, copyright, trade secret or other intellectual
** property right is granted to or conferred upon you by disclosure or
** delivery of the Materials, either expressly, by implication, inducement,
** estoppel or otherwise 
** Some portion of the Materials may be copyrighted by Microsoft Corporation.
*/

#ifndef __DMAC_H__
#define __DMAC_H__



//#include "DMACBITS.H"
#define DMAC_AC97_AUDIO_RCV_FIFO	0x40500040
#define DMAC_AC97_AUDIO_XMIT_FIFO	0x40500040 //(was 0x40500140)
#define DMAC_AC97_AUDIO_MIC_FIFO	0x40500060

#define DMAC_AC97_RCVAB_CMD_MASK	0x6023C000  //0110 00000 01 000 11 11 0 0000000000000
#define DMAC_AC97_XMITAB_CMD_MASK	0x9043C000	//1001 00000 10 000 11 11 0 0000000000000
#define DMAC_AC97_MICAB_CMD_MASK	0x6023C000 	//0110 00000 01 000 11 11 0 0000000000000

#define DESC_ADDRESS_MASK       	0xFFFFFFF0
#define DESC_ADDRESS_STOP_MASK  	(0x1U <<0)

#define DMA_MAP_VALID_MASK  (0x1U << 7)  // Request is mapped to a valid channel indicated by DRCMRx(3:0)



#define DCSR_BUSERRINTR     (0x1U << 0)  // Bus error status bit
#define DCSR_STARTINTR      (0x1U << 1)  // Descriptor fetch status 
#define DCSR_ENDINTR        (0x1U << 2)  // finish status
#define DCSR_STOPINTR       (0x1U << 3)  // stopped status
#define DCSR_REQPEND        (0x1U << 8)  // Request Pending (read-only)
#define DCSR_STARTIRQEN     (0x1U << 21) // Enable the start interrupt (when the descriptor is loaded)
#define DCSR_STOPIRQEN      (0x1U << 29) // Enable the stopped interrupt (when the descriptor is done)
#define DCSR_NOFETCH        (0x1U << 30) // Descriptor fetch mode, 0 = fetch
#define DCSR_RUN            (0x1U << 31) // run, 1=start

#define DCMD_LEN_MASK			0xFFF // mask off the length bits
#define DCMD_LEN_ZERO_MASK		0xFFFFFFFFFFFFF000 //clear the length bits
		
struct DMAC_FRAME_DESCRIPTOR 
{
	unsigned int ddadr;		// address of the next frame descriptor (physical address)
	unsigned int dsadr;		// address of the source  data (physical address)
	unsigned int dtadr;     // address of the destination
	unsigned int dcmd;		// dma command
};


// the dmcd struct is for documentation
struct dcmdRegBits 
{
	unsigned len	     :13;
	unsigned rsv0		 :1;   
	unsigned width		 :2; 
	unsigned size		 :2;
	unsigned endian		 :1;
	unsigned flybyt	 	 :1;
	unsigned flybys	 	 :1;
	unsigned endirqen    :1;
	unsigned startirqen  :1;
	unsigned rsv1        :5;
	unsigned flowtrg     :1;
	unsigned flowsrc     :1;
	unsigned inctrgadd   :1;
	unsigned incsrcadd   :1;
};

union DmaCmdReg// allow bitfields or masks
{

	volatile struct dcmdRegBits DcmdReg ;
	volatile DWORD DcmdDword;
} ;


///////////////////////////////////////////////////////////////////////////////


#endif