📄 rt5621.h
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#define SPK_D_AMP_CTRL_RATIO_100 (0x3<<10) //1.00 Vdd
//Global Clock Control Register(0x42)
#define SYSCLK_SOUR_SEL_MASK (0x1<<15)
#define SYSCLK_SOUR_SEL_MCLK (0x0<<15) //system Clock source from MCLK
#define SYSCLK_SOUR_SEL_PLL (0x1<<15) //system Clock source from PLL
#define PLLCLK_SOUR_SEL_MCLK (0x0<<14) //PLL clock source from MCLK
#define PLLCLK_SOUR_SEL_BITCLK (0x1<<14) //PLL clock source from BITCLK
#define PLLCLK_DIV_RATIO_MASK (0x3<<1)
#define PLLCLK_DIV_RATIO_DIV1 (0x0<<1) //DIV 1
#define PLLCLK_DIV_RATIO_DIV2 (0x1<<1) //DIV 2
#define PLLCLK_DIV_RATIO_DIV4 (0x2<<1) //DIV 4
#define PLLCLK_DIV_RATIO_DIV8 (0x3<<1) //DIV 8
#define PLLCLK_PRE_DIV1 (0x0) //DIV 1
#define PLLCLK_PRE_DIV2 (0x1) //DIV 2
//PLL Control(0x44)
#define PLL_CTRL_M_VAL(m) ((m)&0xf)
#define PLL_CTRL_K_VAL(k) (((k)&0x7)<<4)
#define PLL_CTRL_N_VAL(n) (((n)&0xff)<<8)
//GPIO Pin Configuration(0x4C)
#define GPIO_PIN_MASK (0x1<<1)
#define GPIO_PIN_SET_INPUT (0x1<<1)
#define GPIO_PIN_SET_OUTPUT (0x0<<1)
//Pin Sharing(0x56)
#define LINEIN_L_PIN_SHARING (0x1<<15)
#define LINEIN_L_PIN_AS_LINEIN_L (0x0<<15)
#define LINEIN_L_PIN_AS_JD1 (0x1<<15)
#define LINEIN_R_PIN_SHARING (0x1<<14)
#define LINEIN_R_PIN_AS_LINEIN_R (0x0<<14)
#define LINEIN_R_PIN_AS_JD2 (0x1<<14)
#define GPIO_PIN_SHARING (0x3)
#define GPIO_PIN_AS_GPIO (0x0)
#define GPIO_PIN_AS_IRQOUT (0x1)
#define GPIO_PIN_AS_PLLOUT (0x3)
//Jack Detect Control Register(0x5A)
#define JACK_DETECT_MASK (0x3<<14)
#define JACK_DETECT_USE_JD2 (0x3<<14)
#define JACK_DETECT_USE_JD1 (0x2<<14)
#define JACK_DETECT_USE_GPIO (0x1<<14)
#define JACK_DETECT_OFF (0x0<<14)
#define SPK_EN_IN_HI (0x1<<11)
#define AUX_R_EN_IN_HI (0x1<<10)
#define AUX_L_EN_IN_HI (0x1<<9)
#define HP_EN_IN_HI (0x1<<8)
#define SPK_EN_IN_LO (0x1<<7)
#define AUX_R_EN_IN_LO (0x1<<6)
#define AUX_L_EN_IN_LO (0x1<<5)
#define HP_EN_IN_LO (0x1<<4)
////MISC CONTROL(0x5E)
#define DISABLE_FAST_VREG (0x1<<15)
#define THERMAL_SHUT_DOWN_EN (0x1<<14)
#define SPK_CLASS_AB_OC_PD (0x1<<13)
#define HP_DEPOP_MODE3_EN (0x1<<10)
#define HP_DEPOP_MODE2_EN (0x1<<9)
#define HP_DEPOP_MODE1_EN (0x1<<8)
#define AUXOUT_DEPOP_MODE3_EN (0x1<<6)
#define AUXOUT_DEPOP_MODE2_EN (0x1<<5)
#define AUXOUT_DEPOP_MODE1_EN (0x1<<4)
#define M_DAC_L_INPUT (0x1<<3)
#define M_DAC_R_INPUT (0x1<<2)
#define IRQOUT_INV_CTRL (0x1<<0)
//Psedueo Stereo & Spatial Effect Block Control(0x60)
#define SPATIAL_CTRL_EN (0x1<<15)
#define ALL_PASS_FILTER_EN (0x1<<14)
#define PSEUDO_STEREO_EN (0x1<<13)
#define STEREO_EXPENSION_EN (0x1<<12)
#define GAIN_3D_PARA_L_MASK (0x7<<9)
#define GAIN_3D_PARA_L_1_00 (0x0<<9)
#define GAIN_3D_PARA_L_1_25 (0x1<<9)
#define GAIN_3D_PARA_L_1_50 (0x2<<9)
#define GAIN_3D_PARA_L_1_75 (0x3<<9)
#define GAIN_3D_PARA_L_2_00 (0x4<<9)
#define GAIN_3D_PARA_R_MASK (0x7<<6)
#define GAIN_3D_PARA_R_1_00 (0x0<<6)
#define GAIN_3D_PARA_R_1_25 (0x1<<6)
#define GAIN_3D_PARA_R_1_50 (0x2<<6)
#define GAIN_3D_PARA_R_1_75 (0x3<<6)
#define GAIN_3D_PARA_R_2_00 (0x4<<6)
#define RATIO_3D_L_MASK (0x3<<4)
#define RATIO_3D_L_0_0 (0x0<<4)
#define RATIO_3D_L_0_66 (0x1<<4)
#define RATIO_3D_L_1_0 (0x2<<4)
#define RATIO_3D_R_MASK (0x3<<2)
#define RATIO_3D_R_0_0 (0x0<<2)
#define RATIO_3D_R_0_66 (0x1<<2)
#define RATIO_3D_R_1_0 (0x2<<2)
#define APF_MASK (0x3)
#define APF_FOR_48K (0x3)
#define APF_FOR_44_1K (0x2)
#define APF_FOR_32K (0x1)
//EQ CONTROL(0x62)
#define EN_HW_EQ_BLK (0x1<<15) //HW EQ block control
#define EN_HW_EQ_HPF_MODE (0x1<<14) //High Frequency shelving filter mode
#define EN_HW_EQ_SOUR (0x1<<11) //0:DAC PATH,1:ADC PATH
#define EN_HW_EQ_HPF (0x1<<4) //EQ High Pass Filter Control
#define EN_HW_EQ_BP3 (0x1<<3) //EQ Band-3 Control
#define EN_HW_EQ_BP2 (0x1<<2) //EQ Band-2 Control
#define EN_HW_EQ_BP1 (0x1<<1) //EQ Band-1 Control
#define EN_HW_EQ_LPF (0x1<<0) //EQ Low Pass Filter Control
//EQ Mode Change Enable(0x66)
#define EQ_HPF_CHANGE_EN (0x1<<4) //EQ High Pass Filter Mode Change Enable
#define EQ_BP3_CHANGE_EN (0x1<<3) //EQ Band-3 Pass Filter Mode Change Enable
#define EQ_BP2_CHANGE_EN (0x1<<2) //EQ Band-2 Pass Filter Mode Change Enable
#define EQ_BP1_CHANGE_EN (0x1<<1) //EQ Band-1 Pass Filter Mode Change Enable
#define EQ_LPF_CHANGE_EN (0x1<<0) //EQ Low Pass Filter Mode Change Enable
//AVC Control(0x68)
#define AVC_ENABLE (0x1<<15)
#define AVC_TARTGET_SEL_MASK (0x1<<14)
#define AVC_TARTGET_SEL_R (0x1<<14)
#define AVC_TARTGET_SEL_L (0x0<<14)
typedef enum
{
BOOST_BYPASS,
BOOST_20DB,
BOOST_30DB,
BOOST_40DB
}MIC_BOOST_TYPE;
typedef struct
{
BYTE CodecIndex;
unsigned short int wCodecValue;
}CodecRegister;
typedef enum
{
HW_EQ_LP0_A1=0,
HW_EQ_LP0_H0,
HW_EQ_BP1_A1,
HW_EQ_BP1_A2,
HW_EQ_BP1_H0,
HW_EQ_BP2_A1,
HW_EQ_BP2_A2,
HW_EQ_BP2_H0,
HW_EQ_BP3_A1,
HW_EQ_BP3_A2,
HW_EQ_BP3_H0,
HW_EQ_BP4_A1,
HW_EQ_HP4_H0,
HW_EQ_INPUT_VOL=0x11,
HW_EQ_OUTPUT_VOL,
AVC_CTRL_REG1=0x21,
AVC_CTRL_REG2,
AVC_CTRL_REG3,
AVC_CTRL_REG4,
AVC_CTRL_REG5,
DIG_INTER_REG=0x39,
CLASS_AB_REG=0x44,
CLASS_D_REG=0x46,
}EXT_CODEC_INDEX;
typedef enum
{
POWER_STATE_D0=0,
POWER_STATE_D1,
POWER_STATE_D1_PLAYBACK,
POWER_STATE_D1_RECORD,
POWER_STATE_D2,
POWER_STATE_D2_PLAYBACK,
POWER_STATE_D2_RECORD,
POWER_STATE_D3,
POWER_STATE_D4
}POWER_STATE;
typedef enum
{
DEPOP_MODE1_HP,
DEPOP_MODE2_HP,
DEPOP_MODE3_HP
}DEPOP_MODE;
typedef enum
{
SET_3D_L_GAIN=0,
SET_3D_R_GAIN,
SET_3D_L_RATIO,
SET_3D_R_RATIO,
SET_3D_ENABLE,
SET_3D_DISABLE
}SET_3D_PARA_MODE;
typedef enum
{
RT_WAVOUT_PATH_ALL=0,
RT_WAVOUT_PATH_HP,
RT_WAVOUT_PATH_SPK,
RT_WAVOUT_PATH_AUX,
RT_WAVOUT_PATH_MONO,
RT_WAVOUT_PATH_DAC,
}WAVOUT_PATH;
typedef enum
{
CLUB=0,
DANCE,
LIVE,
POP,
ROCK,
}HW_EQ_PRESET_TYPE;
typedef struct _HW_EQ_PRESET
{
HW_EQ_PRESET_TYPE HwEqType;
unsigned short int EqValue[14];
unsigned short int HwEQCtrl;
}HW_EQ_PRESET;
class RT5621_Codec
{
public:
HardwareContext *m_pHWContext;
RT5621_Codec();
~RT5621_Codec();
BOOL ShadowReadCodec(BYTE Offset, unsigned short int *Data);
BOOL ShadowWriteCodec(BYTE Offset, unsigned short int Data);
BOOL WriteCodecRegMask(BYTE Offset, unsigned short int Data,unsigned short int Mask);
BOOL WriteCodecAdvance(EXT_CODEC_INDEX Ext_Index,unsigned short int Data);
BOOL ReadCodecAdvance(EXT_CODEC_INDEX Index,unsigned short int *Data);
BOOL WriteCodecAdvanceMask(EXT_CODEC_INDEX Ext_Index,unsigned short int Ext_Data,unsigned short int Ext_Data_Mask);
BOOL Init(HardwareContext *HwCxt);
BOOL InitRTCodecReg(void);
BOOL ConfigMicBias(BYTE Mic,BYTE MicBiasCtrl);
BOOL ConfigVmidOutput(BYTE SPK_Type,unsigned short int VMID_RATIO);
BOOL ConfigMicBoost(BYTE Mic,MIC_BOOST_TYPE BoostType);
BOOL EnablePLLPath(BOOL bEnablePLL,unsigned short int K,unsigned short int M,unsigned short int N);
BOOL Enable_ADC_Input_Source(unsigned short int ADC_Input_Sour,BOOL Enable);
void DepopForHP(DEPOP_MODE Depop_mode);
void SaveCodecRegToShadow();
void RestoreRegToCodec();
void SaveCodecExtRegToShadow();
void ReStoreExtRegToCodec();
void DelayMSTime(unsigned int MilliSec);
BOOL ChangeCodecPowerStatus(POWER_STATE power_state);
BOOL EnableAVC(BOOL Enable_AVC);
BOOL Enable_Main_Spatial(BOOL Enable_Main_Spatial);
BOOL Set_3D_Func(SET_3D_PARA_MODE S_3d_para,BYTE para);
BOOL Enable_Pseudo_Stereo(BOOL Enable_Pseudo_Stereo);
BOOL Enable_All_Pass_Filter(BOOL Enable_APF);
BOOL EnableHwEq(HW_EQ_PRESET_TYPE Hw_Eq_Type,BOOL HwEqEnable);
BOOL AudioOutEnable(WAVOUT_PATH WavOutPath,BOOL Mute);
DWORD ProcessAudioMessage(UINT uMsg,DWORD dwParam1,DWORD dwParam2);
BOOL JackDectCtrl(unsigned short int JackDetSel,unsigned short int OutputEnable);
void EnableVref(BOOL VrefEnable);
private:
unsigned short int m_WaveInSampleRate;
unsigned short int m_WaveOutSampleRate;
friend class HardwareContext;
};
#endif //__RTCODEC5621_H__⌨️ 快捷键说明
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