📄 rt5621.h
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#ifndef __RTCODEC5621_H__
#define __RTCODEC5621_H__
#include "wavemain.h"
//Index of Codec Register definition
#define RT5621_RESET 0X00 //RESET CODEC TO DEFAULT
#define RT5621_SPK_OUT_VOL 0X02 //SPEAKER OUT VOLUME
#define RT5621_HP_OUT_VOL 0X04 //HEADPHONE OUTPUT VOLUME
#define RT5621_MONO_AUX_OUT_VOL 0X06 //MONO OUTPUT/AUXOUT VOLUME
#define RT5621_AUXIN_VOL 0X08 //AUXIN VOLUME
#define RT5621_LINE_IN_VOL 0X0A //LINE IN VOLUME
#define RT5621_STEREO_DAC_VOL 0X0C //STEREO DAC VOLUME
#define RT5621_MIC_VOL 0X0E //MICROPHONE VOLUME
#define RT5621_MIC_ROUTING_CTRL 0X10 //MIC ROUTING CONTROL
#define RT5621_ADC_REC_GAIN 0X12 //ADC RECORD GAIN
#define RT5621_ADC_REC_MIXER 0X14 //ADC RECORD MIXER CONTROL
#define RT5621_SOFT_VOL_CTRL_TIME 0X16 //SOFT VOLUME CONTROL TIME
#define RT5621_OUTPUT_MIXER_CTRL 0X1C //OUTPUT MIXER CONTROL
#define RT5621_MICROPHONE_CTRL 0X22 //MICROPHONE CONTROL
#define RT5621_AUDIO_INTERFACE 0X34 //AUDIO INTERFACE
#define RT5621_STEREO_AD_DA_CLK_CTRL 0X36 //STEREO AD/DA CLOCK CONTROL
#define RT5621_COMPANDING_CTRL 0X38 //COMPANDING CONTROL
#define RT5621_PWR_MANAG_ADD1 0X3A //POWER MANAGMENT ADDITION 1
#define RT5621_PWR_MANAG_ADD2 0X3C //POWER MANAGMENT ADDITION 2
#define RT5621_PWR_MANAG_ADD3 0X3E //POWER MANAGMENT ADDITION 3
#define RT5621_ADD_CTRL_REG 0X40 //ADDITIONAL CONTROL REGISTER
#define RT5621_GLOBAL_CLK_CTRL_REG 0X42 //GLOBAL CLOCK CONTROL REGISTER
#define RT5621_PLL_CTRL 0X44 //PLL CONTROL
#define RT5621_GPIO_OUTPUT_PIN_CTRL 0X4A //GPIO OUTPUT PIN CONTROL
#define RT5621_GPIO_PIN_CONFIG 0X4C //GPIO PIN CONFIGURATION
#define RT5621_GPIO_PIN_POLARITY 0X4E //GPIO PIN POLARITY/TYPE
#define RT5621_GPIO_PIN_STICKY 0X50 //GPIO PIN STICKY
#define RT5621_GPIO_PIN_WAKEUP 0X52 //GPIO PIN WAKE UP
#define RT5621_GPIO_PIN_STATUS 0X54 //GPIO PIN STATUS
#define RT5621_GPIO_PIN_SHARING 0X56 //GPIO PIN SHARING
#define RT5621_OVER_TEMP_CURR_STATUS 0X58 //OVER TEMPERATURE AND CURRENT STATUS
#define RT5621_JACK_DET_CTRL 0X5A //JACK DETECT CONTROL REGISTER
#define RT5621_MISC_CTRL 0X5E //MISC CONTROL
#define RT5621_PSEDUEO_SPATIAL_CTRL 0X60 //PSEDUEO STEREO & SPATIAL EFFECT BLOCK CONTROL
#define RT5621_EQ_CTRL 0X62 //EQ CONTROL
#define RT5621_EQ_STATUS 0X64 //EQ STATUS
#define RT5621_EQ_MODE_ENABLE 0X66 //EQ MODE CHANGE ENABLE
#define RT5621_AVC_CTRL 0X68 //AVC CONTROL
#define RT5621_HID_CTRL_INDEX 0X6A //HIDDEN CONTROL INDEX PORT
#define RT5621_HID_CTRL_DATA 0X6C //HIDDEN CONTROL DATA PORT
#define RT5621_VENDOR_ID1 0x7C //VENDOR ID1
#define RT5621_VENDOR_ID2 0x7E //VENDOR ID2
//global definition
#define RT_L_MUTE (0x1<<15) //MUTE LEFT CONTROL BIT
#define RT_L_ZC (0x1<<14) //LEFT ZERO CROSS CONTROL BIT
#define RT_L_SM (0x1<<13) //LEFT SOFTMUTE CONTROL BIT
#define RT_R_MUTE (0x1<<7) //MUTE RIGHT CONTROL BIT
#define RT_R_ZC (0x1<<6) //RIGHT ZERO CROSS CONTROL BIT
#define RT_R_SM (0x1<<5) //RIGHT SOFTMUTE CONTROL BIT
#define RT_M_HP_MIXER (0x1<<15) //Mute source to HP Mixer
#define RT_M_SPK_MIXER (0x1<<14) //Mute source to Speaker Mixer
#define RT_M_MONO_MIXER (0x1<<13) //Mute source to Mono Mixer
#define SPK_CLASS_AB 0
#define SPK_CLASS_D 1
//Mic Routing Control(0x10)
#define MIC1_DIFF_INPUT_CTRL (0x1<<12) //MIC1 different input control
#define M_MIC2_TO_HP_MIXER (0x1<<7) //Mute MIC2 to HP mixer
#define M_MIC2_TO_SPK_MIXER (0x1<<6) //Mute MiC2 to SPK mixer
#define M_MIC2_TO_MONO_MIXER (0x1<<5) //Mute MIC2 to MONO mixer
#define MIC2_DIFF_INPUT_CTRL (0x1<<4) //MIC2 different input control
#define ALL_FIELD 0xffff
#define MHZ11_980 11980000
#define KHZ08_000 8000
#define KHZ11_025 11025
#define KHZ12_000 12000
#define KHZ16_000 16000
#define KHZ22_050 22050
#define KHZ24_000 24000
#define KHZ32_000 32000
#define KHZ44_100 44100
#define KHZ48_000 48000
//ADC Input Mixer Control(0x14)
#define M_MIC1_TO_ADC_L_MIXER (0x1<<14) //Mute mic1 to left channel of ADC mixer
#define M_MIC2_TO_ADC_L_MIXER (0x1<<13) //Mute mic2 to left channel of ADC mixer
#define M_LINEIN_L_TO_ADC_L_MIXER (0x1<<12) //Mute line In left channel to left channel of ADC mixer
#define M_AUXIN_L_TO_ADC_L_MIXER (0x1<<11) //Mute aux In left channel to left channel of ADC mixer
#define M_HPMIXER_L_TO_ADC_L_MIXER (0x1<<10) //Mute HP mixer left channel to left channel of ADC mixer
#define M_SPKMIXER_L_TO_ADC_L_MIXER (0x1<<9) //Mute SPK mixer left channel to left channel of ADC mixer
#define M_MONOMIXER_L_TO_ADC_L_MIXER (0x1<<8) //Mute MONO mixer left channel to left channel of ADC mixer
#define M_MIC1_TO_ADC_R_MIXER (0x1<<6) //Mute mic1 to right channel of ADC mixer
#define M_MIC2_TO_ADC_R_MIXER (0x1<<5) //Mute mic2 to right channel of ADC mixer
#define M_LINEIN_R_TO_ADC_R_MIXER (0x1<<4) //Mute lineIn right channel to right channel of ADC mixer
#define M_AUXIN_R_TO_ADC_R_MIXER (0x1<<3) //Mute aux In right channel to right channel of ADC mixer
#define M_HPMIXER_R_TO_ADC_R_MIXER (0x1<<2) //Mute HP mixer right channel to right channel of ADC mixer
#define M_SPKMIXER_R_TO_ADC_R_MIXER (0x1<<1) //Mute SPK mixer right channel to right channel of ADC mixer
#define M_MONOMIXER_R_TO_ADC_R_MIXER (0x1<<0) //Mute MONO mixer right channel to right channel of ADC mixer
//Output Mixer Control(0x1C)
#define SPKOUT_N_SOUR_MASK (0x3<<14)
#define SPKOUT_N_SOUR_LN (0x2<<14)
#define SPKOUT_N_SOUR_RP (0x1<<14)
#define SPKOUT_N_SOUR_RN (0x0<<14)
#define SPK_OUTPUT_CLASS_AB (0x0<<13)
#define SPK_OUTPUT_CLASS_D (0x1<<13)
#define SPK_CLASS_AB_S_AMP (0x0<<12)
#define SPK_CALSS_AB_W_AMP (0x1<<12)
#define SPKOUT_INPUT_SEL_MASK (0x3<<10)
#define SPKOUT_INPUT_SEL_MONOMIXER (0x3<<10)
#define SPKOUT_INPUT_SEL_SPKMIXER (0x2<<10)
#define SPKOUT_INPUT_SEL_HPMIXER (0x1<<10)
#define SPKOUT_INPUT_SEL_VMID (0x0<<10)
#define HPL_INPUT_SEL_HPLMIXER (0x1<<9)
#define HPR_INPUT_SEL_HPRMIXER (0x1<<8)
#define MONO_AUX_INPUT_SEL_MASK (0x3<<6)
#define MONO_AUX_INPUT_SEL_MONO (0x3<<6)
#define MONO_AUX_INPUT_SEL_SPK (0x2<<6)
#define MONO_AUX_INPUT_SEL_HP (0x1<<6)
#define MONO_AUX_INPUT_SEL_VMID (0x0<<6)
//Micphone Control define(0x22)
#define MIC1 1
#define MIC2 2
#define MIC_BIAS_90_PRECNET_AVDD 1
#define MIC_BIAS_75_PRECNET_AVDD 2
#define MIC1_BOOST_CTRL_MASK (0x3<<10)
#define MIC1_BOOST_CTRL_BYPASS (0x0<<10)
#define MIC1_BOOST_CTRL_20DB (0x1<<10)
#define MIC1_BOOST_CTRL_30DB (0x2<<10)
#define MIC1_BOOST_CTRL_40DB (0x3<<10)
#define MIC2_BOOST_CTRL_MASK (0x3<<8)
#define MIC2_BOOST_CTRL_BYPASS (0x0<<8)
#define MIC2_BOOST_CTRL_20DB (0x1<<8)
#define MIC2_BOOST_CTRL_30DB (0x2<<8)
#define MIC2_BOOST_CTRL_40DB (0x3<<8)
#define MICBIAS_VOLT_CTRL_MASK (0x1<<5)
#define MICBIAS_VOLT_CTRL_90P (0x0<<5)
#define MICBIAS_VOLT_CTRL_75P (0x1<<5)
#define MICBIAS_SHORT_CURR_DET_MASK (0x3)
#define MICBIAS_SHORT_CURR_DET_600UA (0x0)
#define MICBIAS_SHORT_CURR_DET_1200UA (0x1)
#define MICBIAS_SHORT_CURR_DET_1800UA (0x2)
//Audio Interface(0x34)
#define SDP_MASTER_MODE (0x0<<15)
#define SDP_SLAVE_MODE (0x1<<15)
#define I2S_PCM_MODE (0x1<<14) //PCM 0:mode A ,1:mode B
//Non PCM 0:Normal SADLRCK/SDALRCK,1:Invert SADLRCK/SDALRCK
#define MAIN_I2S_BCLK_POL_CTRL (0x1<<7) //0:Normal 1:Invert
#define ADC_DATA_L_R_SWAP (0x1<<5) //0:ADC data appear at left phase of LRCK
//1:ADC data appear at right phase of LRCK
#define DAC_DATA_L_R_SWAP (0x1<<4) //0:DAC data appear at left phase of LRCK
//1:DAC data appear at right phase of LRCK
//Data Length Slection
#define I2S_DL_MASK (0x3<<2) //main i2s Data Length mask
#define I2S_DL_16 (0x0<<2) //16 bits
#define I2S_DL_20 (0x1<<2) //20 bits
#define I2S_DL_24 (0x2<<2) //24 bits
#define I2S_DL_32 (0x3<<2) //32 bits
//PCM Data Format Selection
#define I2S_DF_MASK (0x3) //main i2s Data Format mask
#define I2S_DF_I2S (0x0) //I2S FORMAT
#define I2S_DF_RIGHT (0x1) //RIGHT JUSTIFIED format
#define I2S_DF_LEFT (0x2) //LEFT JUSTIFIED format
#define I2S_DF_PCM (0x3) //PCM format
//Stereo AD/DA Clock Control(0x36h)
#define I2S_PRE_DIV_MASK (0x7<<12)
#define I2S_PRE_DIV_1 (0x0<<12) //DIV 1
#define I2S_PRE_DIV_2 (0x1<<12) //DIV 2
#define I2S_PRE_DIV_4 (0x2<<12) //DIV 4
#define I2S_PRE_DIV_8 (0x3<<12) //DIV 8
#define I2S_PRE_DIV_16 (0x4<<12) //DIV 16
#define I2S_PRE_DIV_32 (0x5<<12) //DIV 32
#define I2S_SCLK_DIV_MASK (0x7<<9)
#define I2S_SCLK_DIV_1 (0x0<<9) //DIV 1
#define I2S_SCLK_DIV_2 (0x1<<9) //DIV 2
#define I2S_SCLK_DIV_3 (0x2<<9) //DIV 3
#define I2S_SCLK_DIV_4 (0x3<<9) //DIV 4
#define I2S_SCLK_DIV_6 (0x4<<9) //DIV 6
#define I2S_SCLK_DIV_8 (0x5<<9) //DIV 8
#define I2S_SCLK_DIV_12 (0x6<<9) //DIV 12
#define I2S_SCLK_DIV_16 (0x7<<9) //DIV 16
#define I2S_WCLK_DIV_PRE_MASK (0xF<<5)
#define I2S_WCLK_PRE_DIV_1 (0x0<<5) //DIV 1
#define I2S_WCLK_PRE_DIV_2 (0x1<<5) //DIV 2
#define I2S_WCLK_PRE_DIV_3 (0x2<<5) //DIV 3
#define I2S_WCLK_PRE_DIV_4 (0x3<<5) //DIV 4
#define I2S_WCLK_PRE_DIV_5 (0x4<<5) //DIV 5
#define I2S_WCLK_PRE_DIV_6 (0x5<<5) //DIV 6
#define I2S_WCLK_PRE_DIV_7 (0x6<<5) //DIV 7
#define I2S_WCLK_PRE_DIV_8 (0x7<<5) //DIV 8
//........................
#define I2S_WCLK_DIV_MASK (0x7<<2)
#define I2S_WCLK_DIV_2 (0x0<<2) //DIV 2
#define I2S_WCLK_DIV_4 (0x1<<2) //DIV 4
#define I2S_WCLK_DIV_8 (0x2<<2) //DIV 8
#define I2S_WCLK_DIV_16 (0x3<<2) //DIV 16
#define I2S_WCLK_DIV_32 (0x4<<2) //DIV 32
#define ADDA_FILTER_CLK_SEL_256FS (0<<1) //256FS
#define ADDA_FILTER_CLK_SEL_384FS (1<<1) //384FS
#define ADDA_OSR_SEL_64FS (0) //64FS
#define ADDA_OSR_SEL_128FS (1) //128FS
//Power managment addition 1 (0x3A),0:Disable,1:Enable
#define PWR_MAIN_I2S_EN (0x1<<15)
#define PWR_ZC_DET_PD_EN (0x1<<14)
#define PWR_MIC1_BIAS_EN (0x1<<11)
#define PWR_SHORT_CURR_DET_EN (0x1<<10)
#define PWR_SOFTGEN_EN (0x1<<8)
#define PWR_DEPOP_BUF_HP (0x1<<6)
#define PWR_HP_OUT (0x1<<5)
#define PWR_HP_AMP (0x1<<4)
#define PWR_DEPOP_BUF_AUX (0x1<<2)
#define PWR_AUX_OUT (0x1<<1)
#define PWR_AUX_AMP (0x1)
//Power managment addition 2(0x3C),0:Disable,1:Enable
#define PWR_CLASS_AB (0x1<<15)
#define PWR_CLASS_D (0x1<<14)
#define PWR_VREF (0x1<<13)
#define PWR_PLL (0x1<<12)
#define PWR_THERMAL_SD (0x1<<11)
#define PWR_DAC_REF_CIR (0x1<<10)
#define PWR_L_DAC_CLK (0x1<<9)
#define PWR_R_DAC_CLK (0x1<<8)
#define PWR_L_ADC_CLK_GAIN (0x1<<7)
#define PWR_R_ADC_CLK_GAIN (0x1<<6)
#define PWR_L_HP_MIXER (0x1<<5)
#define PWR_R_HP_MIXER (0x1<<4)
#define PWR_SPK_MIXER (0x1<<3)
#define PWR_MONO_MIXER (0x1<<2)
#define PWR_L_ADC_REC_MIXER (0x1<<1)
#define PWR_R_ADC_REC_MIXER (0x1)
//Power managment addition 3(0x3E),0:Disable,1:Enable
#define PWR_MAIN_BIAS (0x1<<15)
#define PWR_AUXOUT_R_VOL_AMP (0x1<<14)
#define PWR_AUXOUT_L_VOL_AMP (0x1<<13)
#define PWR_SPK_R_OUT (0x1<<12)
#define PWR_SPK_RN_OUT (0x1<<11)
#define PWR_HP_L_OUT_VOL (0x1<<10)
#define PWR_HP_R_OUT_VOL (0x1<<9)
#define PWR_LINEIN_L_VOL (0x1<<7)
#define PWR_LINEIN_R_VOL (0x1<<6)
#define PWR_AUXIN_L_VOL (0x1<<5)
#define PWR_AUXIN_R_VOL (0x1<<4)
#define PWR_MIC1_FUN_CTRL (0x1<<3)
#define PWR_MIC2_FUN_CTRL (0x1<<2)
#define PWR_MIC1_BOOST_MIXER (0x1<<1)
#define PWR_MIC2_BOOST_MIXER (0x1)
//Additional Control Register(0x40)
#define AUXOUT_SEL_DIFF (0x1<<15) //Differential Mode
#define AUXOUT_SEL_SE (0x1<<15) //Single-End Mode
#define SPK_AB_AMP_CTRL_MASK (0x7<<12)
#define SPK_AB_AMP_CTRL_RATIO_225 (0x0<<12) //2.25 Vdd
#define SPK_AB_AMP_CTRL_RATIO_200 (0x1<<12) //2.00 Vdd
#define SPK_AB_AMP_CTRL_RATIO_175 (0x2<<12) //1.75 Vdd
#define SPK_AB_AMP_CTRL_RATIO_150 (0x3<<12) //1.50 Vdd
#define SPK_AB_AMP_CTRL_RATIO_125 (0x4<<12) //1.25 Vdd
#define SPK_AB_AMP_CTRL_RATIO_100 (0x5<<12) //1.00 Vdd
#define SPK_D_AMP_CTRL_MASK (0x3<<10)
#define SPK_D_AMP_CTRL_RATIO_175 (0x0<<10) //1.75 Vdd
#define SPK_D_AMP_CTRL_RATIO_150 (0x1<<10) //1.50 Vdd
#define SPK_D_AMP_CTRL_RATIO_125 (0x2<<10) //1.25 Vdd
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